Research Of High Performance Frequency Dividers For PLL Application

The flourishing of ubiquitous wireless communication networks has significantly promoted the development of complex RF systems.Fully-integrated RF circuits,including dividers,have been playing a key role in such systems.The performances of the divider is closely related to the maximum frequency that the frequency synthesizer can work and its frequency range.The main content of this dissertation is the design and optimization of divider in frequency synthesizer,especially the design with wide frequency range and high frequency division ratio.This dissertation first introduces the basic knowledge of PLL frequency synthesizer,studies the function of the divider and the operational principle of the rest parts,as well as the loop characteristics of the PLL,followed by the noise transmission characteristics of each module in the loop are analyzed.After that,we study the key technologies of the divider design,summarize the existing modules and cell topology,and compare various structural features and application.The design and optimization of high performances frequency dividers includes two designs.A 50MHz-6GHz divider is designed based on TSMC 65nm CMOS technology,which is further extended to 20GHz operation with a frequency division ratio of 21?511 using GF 65nm CMOS technology.Finally,the divider is applied to the current controlled phase-locked loop(CCPLL)using active inductor oscillator and transformer.The system level application and design process of the divider are introduced.Schematic level simulation,post-layout simulation as well as fabricated are performed using the GSMC 0.13?m CMOS process.The frequency range of the PLL is about 753MHz-1.6GHz with a power consumption 17.5mW.The area of the whole chip is about 545?m x400p?m.