Research On Design And UVM Verification Of Recurrent Neural Network

With the increase of available data,the improvement of equipment computing power and the innovation of algorithms,artificial neural networks have achieved a lot of remarkable achievements in practical applications.Among them,LSTM,as a variant of RNN,has made breakthroughs in many problems related to sequence data due to the successful resolution of long-term dependencies.Researching and designing ASIC accelerators for this network is of great importance to make full use of its advantages.Also,given the important role of verification for integrated circuit development,a designed accelerator must be verified to demonstrate that it does not deviate from the design goals and that the functionality is correct.This thesis first introduces the characteristics of this class of neural network with the conventional RNN as the representative,and explains the causes of the long-term dependencies.After that,the network structure of LSTM is introduced,and the computational procedure of its forward propagation algorithm is analyzed in detail,which provides a theoretical basis for the subsequent design work.In addition,this thesis also includes a description of several key core concepts in UVM,introduces the methods and tools that will be used frequently in subsequent verification tasks.Then,matrix-vector multiplication,activation function and element-wise multiplication in the LSTM network are taken as the design focus.The implementation,data format and accuracy requirement of each calculation are carefully considered,after taking into account intensive computation and large amount of data,optimization schemes such as increasing computational parallelism and extending bandwidth are proposed.Before the implementation,a model for the accelerator is built using SystemC to check the feasibility.The formal design work is then started based on the selected solution to complete the circuit details.The logic synthesis of the design code results in a gate-level netlist containing 223206 instances and 2.08 million logic gates.After the design is completed,according to the standard of UVM,with its rich and powerful verification functions,the testbenches are built for each module in the design,and the functional verification of each module is carried out to detect the defects in the design process and correct the errors.After that,based on the verification work at the module level,integration and expansion are carried out to build a verification platform suitable for the entire LSTM network system.In the system-level verification process,the simulation is run multiple times,the results are checked in the testbench automatically,and the data information under different conditions is statistically analyzed to confirm the behavior of the accelerator.In addition,a handwritten digit recognition algorithm is run using the accelerator.When the clock frequency is 100 MHz,the accelerator can calculate 1645 images in the MNIST data set per second.The recognition accuracy rate is 98%,which is the same as the software implementation,and the maximum numerical error is only 0.107.Through the verification process of these two parts,it is finally determined that the designed hardware accelerator can correctly and effectively improve the efficiency of the LSTM forward propagation algorithm,achieve the expected goal.