FPGA-Based Design And Implementation Of Energy-Efficienct LSTM Prediction Accelerator

Today,artificial intelligence has become one of the most important disciplines in computer applications.Due to its strong learning and processing capabilities in many areas,artificial intelligence technology has gradually replaced humans in various prac-tical applications to accomplish tasks that required a lot of manpower.As an important method for the artificial intelligence realization,machine learning is becoming more and more important for researchers today,and it is also widely used in industry,such as face recognition,speech recognition,machine translation,and content recommenda-tion.As a model for simulating the human brain,the neural networks have achieved excellent results in practical applications,and thus become the most commonly used model in the field of machine learning.There are many types of neural networks.At present,the most popular neural net-work models include DNNs,CNNs,and LSTMs.LSTM networks are widely used in speech recognition,semantic analysis,and image recognition due to its characteristics.An LSTM network has a large number of connections,which means large-scale param-eters and complex calculation process.Therefore,the research on high performance and low power consumption for the LSTM network is the current hotspot,and implementing a neural network accelerator by using low-power hardware is an effective solution.As a hardware acceleration method,FPGA's high performance and low power con-sumption make it widely used,and its programmable and reconfigurable features also help developers to implement hardware logic more efficiently.This paper presents the hardware implementation design of LSTM network prediction algorithm on FPGA.The main tasks include:1.Analyze the operation logic of the prediction part of the LSTM neural network,decompose it into different operation modules,and analyze the algorithm charac-teristics of each module.2.Design an FPGA hardware unit for each operation module.Use pipeline method to speed up the computation process in parallel to increase the throughput rate.And finally implement the hardware accelerator design of LSTM neural network3.For a large-scale LSTM network,it requires a large amount of storage resources.This paper uses a pruning-retraining method to compress the parameters of large-scale LSTM,and designs a sparse neural network accelerator based on the LSTM network after pruning.4.At experiment part,this paper compares FPGA-based regular/sparse LSTM net-work accelerators with the CPU platform to test performance such as computa-tional throughput and power consumption,and analyzes the resource consump-tion of the FPGA hardware implementation;in addition,data sets were used to test the effect of the pruning method on the prediction accuracy of the LSTM neural network.