The Optimized Design And Application Of Compressor-based Approximate Multiplier

In the past decades,the semiconductor industry has achieved rapid development under the guidance of Moore's law.But in the deep submicron size,the focus of chip design has changed from the traditional pursuit of circuit performance improvement to the comprehensive consideration of performance and power consumption.On the other hand,some error-tolerant applications such as data mining and deep learning,have developed rapidly.Meanwhile these applications are compute-intensive and consume much power.With slight imprecision in computation,they can still obtain useful and efficient results,which makes approximate computation a promising method to design the energy-efficient systems for these applications.Multiplier is one of the most commonly used arithmetic blocks.The use of approximate multipliers can bring considerable improvements to the overall performance and power consumption of the system.Thus,more and more attention has been paid to the design of approximate multipliers.It is noteworthy that partial product reduction consumes a great deal of area and power because of the massive use of full adders(3/2 compressor).Therefore,much effort has been put on the improvement of approximate compressors.Replacing some accurate compressors with approximate compressors can significantly reduce the hardware overhead.In the partial product reduction stage,how to arrange the approximate compressors and exact compressors will also have a significant impact on the overall performance.However,there is not a lot of research on this issue.The main contributions of the paper are:Four basic high accuracy approximate compressors are proposed and combined to form higher order approximate compressors.A novel partial product matrix compression strategy is proposed.As few accurate compressors as possible are placed in effective positions to ensure a limited loss of accuracy.The above two innovations are integrated into the design of 8-bit and 16-bit approximate multiplier.Compared with the designs using other compression strategies,the proposed approximate multiplier can slightly reduce the hardware overhead and further improve the accuracy,which proves the effectiveness of the optimized compression strategy.The proposed 8-bit approximate multiplier has the smallest mean relative error distance and delay,compared to the state-of-the-art.The rest of the metrics also exceed most existing designs.The area,delay,mean relative error distance and normalized mean error distance of the proposed 16-bit approximate multiplier are the smallest.In addition,the proposed multiplier shows on average 4.11% and 9.13% reduction in error rate and power consumption.Finally,the proposed approximate multiplier is applied to image filtering and image multiplication.The peak signal-to-noise ratios of the output images in the two applications are greater than 38.5 dB and 42 dB respectively,and the structural similarity indices are both close to 1.Compared with the image processed by the accurate multiplier,the differences are slight and can be accepted by human eyes.In summary,the proposed compression strategy gives a more effective allocation of exact and approximate compressors.The proposed approximate multiplier exceeds most of the existing designs,reaching the level of advanced design,and it also shows the effectiveness in some image processing applications.