Research And Design Of Arithmetic Logic Unit Based On Approximate Calculation

With the rapid development of 5G,Artificial Intelligence,Internet of Things and other technologies,mankind has entered the era of big data.Facing with increasingly huge computing needs,new technologies are urgently needed to break through the original computing bottleneck.Arithmetic Logic Unit(ALU)is one of the most important and commonly used parts in processor,so the performance of ALU directly affects the performance of CPU.The traditional precise computing circuits have some problems such as high complexity and heavy hardware consumption.Approximate computing can effectively reduce the power consumption,delay and area of the computing circuits,providing a new possibility to optimize the design of ALU.In this thesis,the importance and significance of approximate computing in ALU design are briefly described,and the research status of approximate computing is introduced in detail.The addition circuits are the most basic computing circuits in ALU,and the realization of multiplication circuits and division circuits all depend on addition circuits.In addition,most of the instructions in the computer are addition and subtraction instructions,so the optimization of addition circuits play a very important role in improving the performance of ALU.In this thesis,approximate computing technology is applied to the design of adders,and a new dynamic segment approximate adder is proposed.The performance of the adder is improved by taking advantage of the fact that the length of the carry propagation chain in the addition is shorter than the width of the addition itself.This thesis first analyzes the probability distribution of carry propagation chain length in addition.Then introduces the basic principle and design scheme of the approximate adder in detail,and analyzes its performance theoretically.The hardware performance of the proposed approximate adders is simulated and the calculation accuracy is analyzed by using EDA software and program modelings.The experimental results show that,compared with the traditional precise adders and the existing approximate adders,the approximate adders proposed in this thesis have better performance in delay,power-delay product(PDP),and area-delay product(ADP),and other aspects.Especially in terms of delay,compared with the traditional ripple-carry adder,its delay is reduced by 80.38%.In precision parameters,such as the error rate(ER),mean error distance(MED),normalized mean error distance(NMED),the designs have also been significantly improved.In order to optimize the circuit area of the approximate adder,two approximate full adders,AFA-1 and AFA-2,are designed.The results show that the circuit consumption of dynamic segment adder can be effectively reduced by using approximate full adder.Finally,the designed approximate adder is applied to error-tolerant systems such as audio and image processing to verify the practicability and effectiveness of the design in practical applications.Experimental results show that the processing results of the dynamic segment approximate adder presented in this paper are not significantly different from the processing results of the accurate computing adder,and maintain a high consistency,which can meet the practical needs of daily use.In general,the dynamic segment approximate adders designed in this thesis have certain advantages over the existing design schemes in terms of hardware performance and calculation accuracy,and have certain practicability and effectiveness in error-tolerant applications such as audio and image processing.Approximate computing has increasingly important advantages in digital signal processing,image processing and other aspects,and has shown great potential in the current very popular machine learning,artificial intelligence and other fields,and will certainly have an important impact on the future processor design.