Design Of Majority Logic(ML) Based Arithmetic Operation Unit

As the feature size of current IC technology is approaching to 1nm,quantum effects begin to affect the motion of electrons,thus devices face failure.Therefore,emerging technologies such as nanotechnologies based on majority logic(ML),should be investigated as promising alternative for current Complementary Metal Oxide Semiconductor(CMOS).On the one hand,the development of the financial field and the commercial field not only requires high precision,but also requires high performance,thus the existing decimal arithmetic unit design faces challenges.On the other hand,the power consumption of arithmetic operations has become a main constraint on the development of integrated circuits.Approximate computing as a low-power technology further reduces power consumption and delay by combining with emerging nanotechnology.Therefore,this thesis based on majority logic studied from two perspectives: high-precision decimal arithmetic units for financial applications and low-power approximate arithmetic units for error-tolerant applications.For high-precision decimal arithmetic units,this thesis proposed a BCD adder design method based on the characteristics of ML.This method used a carry lookahead structure to redefine decimal carry outputs in the carry correction module,to make binary results of multi-bit decimal adders being generated in parallel,consequently reducing critical paths and delay.Furthermore,decimal adders were designed according to binary adders.This work not only theoretically compared their area complexity and delay complexity,but also verified the feasibility and advantages using QCADesigner tool.For approximate arithmetic units,the thesis proposed approximate adders and approximate multipliers based on ML.For adders,the thesis proposed a 1-bit approximate full adder and 2-bit approximate full adders based on 1-bit approximate full adders and logic reduction.Moreover,multi-bit approximate full adders were proposed by cascading designs with better performance.For multipliers,this work designed approximate multipliers from partial product generation,complement bits,approximate compressors and partial product reduction circuits.Especially,the work evaluated the impact of compensation bits on errors by defining the impact factor and analyzing its properties,to introduce compensation bits reasonably.Compared with the existing designs,proposed approximate designs had less delay and lower hardware complexity.To verify the reliability,approximate designs were also applied to image processing applications.