Design And Implementation Of Low Power Multiplier Based On Approximate Computing

Multiplication has always been an indispensable digital logic operation in digital signal processing,and it is also the main evaluation index to measure the computing performance of many digital signal processor chips.On the one hand,in order to achieve higher accuracy,digital signal processors usually use floating-point multipliers instead of fixed-point multipliers in operations.On the other hand,in recent years,in fault-tolerant applications such as deep neural networks and some image processing,the power consumption of circuits can be reduced and the computing performance can be improved by reducing the accuracy of some calculations.Aiming at the above application fields,based on a thorough investigation of the approximate calculation theory and the circuit structure of the multiplier,this paper studies the design and optimization methods of the approximate multiplier.First,the basic principle and general design method of the multiplier based on approximate calculation are studied,and the design of the main functional modules of the multiplier and the corresponding error analysis are completed.Secondly,in the design of the partial product generation and compression circuit of the multiplier,an approximate 4-2 compression operation unit based on the AND gate and the OR gate is proposed,and the partial product compression method is optimized.Third,according to the design method of the approximate multiplier proposed in this paper,three kinds of 16-bit approximate multiplier circuits are designed and implemented.Based on this,these approximate multipliers are analyzed and compared using a comprehensive error analysis method.The approximate multiplier proposed in this paper is simulated,synthesized,and physically designed in a 28 nm process.The experimental results show that compared with the traditional accurate calculation multiplier,the approximate multiplier designed in this paper reduces the area by 49.96% and reduces the circuit delay 65.96%,75.44% reduction in power consumption.In image processing application system verification,this paper applies the three approximate multipliers designed for image sharpening and image edge detection.Simulation results show that the proposed approximation multiplier achieves image processing sharpening and edge detection with higher quality.In the image sharpening process,the PSNR value and SSIM value of the image after design 3 are the highest;the SSIM value of the image after design 2 is increased by 0.42 compared with design1.In image edge detection,the processing result of Design 3 is similar to that of the accurate multiplier,while Design 1 and Design 2 are the best results in PSNR and SSIM evaluation,respectively.The research and experimental results show that the multiplier designed based on the approximation theory can significantly reduce the circuit area and operation power,improve processing speed,and effectively control calculation errors.It has certain application prospects in image processing and other fields.