Research On Electrostatic Protection Regime Based On Improved LIGBT Structure

Electrostatic discharge(ESD)is one of the reasons that affect the reliability of integrated circuits.Therefore,effective ESD protection measures is required for the integrated circuit.This paper firstly explains the basic ESD protection principle,and proposes the ESD protection requirements based on the ESD protection window,and determines the theoretical value corresponding to the key parameters.Then it introduces the conventional ESD protection ways and analyzes the working mechanism of the corresponding protective device(including lateral insulated gate bipolar transistor,LIGBT).On this basis,this paper has made the following improvements to the following problems in the application of conventional LIGBT for ESD protection:(1)For the conventional LIGBT structure,it has a strong current processing capability under ESD stress,but there is a problem that the design window is large due to high turn-on voltage and low holding voltage.Then a novel ESD protection device with embedded P-region LIGBT is proposed.The structure changes the breakdown position of by adding p-zone,which reduces the trigger voltage of the device;and an extra parasitic transistor capable of clamping voltage is introduced inside the structure,which weakens the positive feedback effect by the shunting of the new parasitic transistor to increase the holding voltage.Using MEDICI tool under the same simulation conditions,compared with the traditional LIGBT structure,the simulation results show that the protection characteristics of the novel structure have been greatly improved,and the trigger voltage is reduced by 61%,the holding voltage is increased by more than 2 times,and the secondary breakdown current is increased by 8% compared with the conventional LIGBT.Thus,a smaller ESD design window of the structure and a trade-off between current bleed capability and latch-up resistance is achieved.(2)This paper also proposes a new structure of internal NMOS-triggered LIGBT device.The advantage of using an NMOS structure introduced at the source to trigger earlier than a reverse bias PN junction,,so that the trigger voltage is reduced.A new parasitic transistor that can clamp the voltage is introduced into the device,so that the holding voltage is increased.The simulation results show that under the same simulation conditions,compared with the traditional LIGBT,the trigger voltage is low,the holding voltage is improved,and the ESD robustness of the device is still maintained at a high level.(3)In this paper,an improved ESD protection device LIGBT structure with embedded floating N+ region is designed.Due to the existence of floating N+,it modulates the distribution of electric field at the P-body/N-epi metallurgical junction of the device at trigger state,which makes the structure more susceptible to avalanche breakdown,thus the trigger voltage is low.On the one hand,the floating N+ region is used to reduce the efficiency of P+ doping to implant minority carriers(holes)into N-epi,which can help reduce the current benefit of the parasitic PNP transistor,thereby the holding voltage is high.On the other hand,adding a floating N+ region means increasing the equivalent doping concentration of the base region,which can further improve the holding voltage of the device.