Design Of Column-Level Sigma-Delta ADC For Fluorescence Detection Biochips

With the development of bio-fluorescence detection technology,the requirements of column-level analog-to-digital converters are increased in the readout circuit.Column-level ADCs with high precision,low power consumption and small size become an important development direction.Traditional columnlevel ADCs are difficult to meet the needs of fluorescence detection.A compatible column-level Sigma Delta ADC is designed for fluorescence detection in this thesis as the main task.The basic principles of ADCs are introduced first in this thesis.Then the demands of the column-parallel operation mode are analyzed,and the principles and features of Sigma Delta ADC are discussed.Based on this,a column-parallel second-order single-loop single-bit quantized Sigma Delta ADC is designed in this thesis according to the design demands of the application.The Matlab Simulink tool is used to perform system modeling and simulation of the modulator,select the appropriate structural parameters and analyze the impact of non-ideal factors.An inverter-based integrator is designed in the modulator to reduce the area and power consumption of the circuit to meet the requirements of the column-parallel operation.A single bit quantizer is implemented using a dynamic latched comparator.For large arrays of DC detection,incremental mode of operation is used.The digital decimation filter consists of a counter and an accumulator,by which the complexity is greatly reduced compared with a conventional digital decimation filter.Digital correlated double sampling is also used to reduce the effects of circuit dc offset.The schematic and layout are designed in TSMC 0.35?m CMOS process,and the area of the overall ADC is 15?m×(700+1262)?m,which can meet the column-parallel readout circuit requirements of 15?m column width.The simulation results of the ADC show that 74.9dB SNDR and 12.15 bits ENOB are achieved,under the condition of 3.3V voltage supply,10 MHz sampling frequency,and 11.29 KHz,-6dBFS sine signal.The DNL is-0.62LSB/+0.5LSB,and the INL is-0.39LSB/+1.73 LSB for 12-bit digital output.The requirements of design specifications are satisfied by the circuit designed in this thesis according to the simulation results.