Research On The Low Power Incremental ??ADC

In certain application fields,the DC analog signal needs to be converted into digital signal.Therefore,the ?? ADC which uses the oversampling technology and noise shaping technology was choosed to study in this thesis.Based on the characteristics of DC signal detection,the incremental working mode was chosen,and a low-power incremental second-order ?? ADC was designed.At first,the author analyzed the basic principle of analog-to-digital converter,and the theoretical basis of oversampling technology and noise shaping technology was introduced.Secondly,the application characteristics of DC detection and the principle of incremental ?? ADC was discussed.Based on the requirements of design indicators,the structure of the ?? ADC modulator was choosed and determined to use the second-order incremental ?? ADC as the ADC structure of this work.Modulator system modeling and simulation were conducted by using MATLAB Simulink,the system coefficients were selected,and the influence of non-ideal effects on the system was analyzed.Based on the results of behavioral simulations,the ADC circuit was designed.In addition,in order to facilitate the reduction in ADC power consumption,the modulator integrator was designed with low power consumption.The current consumption of the op-amp during the sampling phase was reduced while maintaining the modulator performance.The ADC was operated in an incremental working mode,and was reset every 128 clock cycles.The digital decimation filter was comprised of two-stage digital integrator cascades,including a counter and an accumulator.In comparison to digital filter of the traditional ?? ADC,the circuit complexity was reduced.In this thesis,the ADC was designed based on SMIC 0.18 ?m CMOS process.The simulation results show that with a power supply voltage of 1.8 V and clock frequency of5 MHz,the ADC achieves 80.8 d B SNDR and 13.12 bit ENOB in this thesis.The power consumption of the entire ADC is 189 ?W,the simulation results demonstrate that the indicators of the ADC designed in this thesis satisfy the design requirements.