Research And Design Of Low Power And High Stability CL-LDO For SoC

The power management unit in the system-on-chip（SoC）not only needs to output a stable power supply voltage,but also reduces the quiescent current of the system and prolongs the battery life.As an important part of power management module,low dropout regulator（LDO）is widely used in SoC because of its simple structure,stable output voltage and high PSRR.Capacitors-Less LDO（CL-LDO）are easy to integrate on-chip,and have small layout area and low cost,so they have become a hot research direction in the current LDO field.This paper focuses on the high static power consumption of the bandgap reference voltage of the traditional LDO,the influence of the reference voltage by the power supply ripple noise,the poor loop stability and insufficient transient response performance of CL-LDO。A low power and high stability CL-LDO using sub threshold CMOS voltage reference is designed.The main work and innovations of this paper are as follows:（1）A CMOS voltage reference with high PSRR in sub-threshold region is studied and designed.By adopting pre-regulator technology and output low-pass filter,the circuit can still maintain a high PSRR in a wide frequency range.In addition,the MOSFET substrate voltage driving technology is used to design the reference voltage correction circuit to reduce the deviation of the reference voltage at different process angles.The circuit is designed based on SMIC 110 nm CMOS process.The simulation results show that under1.5V power supply voltage and TT process angle,the reference voltage is 542.63 m V and the start-up time is 1ms.Within the temperature range of-30～80 ℃,the temperature coefficient of the reference voltage is 37.7 ppm/℃.The PSRR of the circuit is-102.41 d B at 1k Hz.（2）A low power and high stability CL-LDO applied for SOC is studied and designed.By adopting Miller capacitance multiplication compensation and zero-pole tracking compensation technology,the LDO has good loop stability in the full load range.In addition,slew rate enhancement circuit is used to dynamically adjust the gate voltage of power transistor,which improves the transient response characteristics of LDO.The circuit is designed based on SMIC 110 nm CMOS process.The simulation results show that under the power supply voltage of 1.5V and TT process angle,the output voltage of LDO is1.21 V and the static current is 35.67μA.The minimum phase margin in the full load range is 85.19°.When the load current steps from 1m A to 50 m A at 1μs,the undershoot amplitude of the output voltage is 96.69 m V,the overshoot amplitude is 102.35 m V,and the maximum adjustment time is 6.3μs.The designed CL-LDO has the advantages of low static power consumption,small on-chip area and high stability.It can provide stable power supply voltage for circuit modules such as data converter,oscillator and has a certain application prospect.