Research And Design Of Low-power Fast-transient Response LDO

With the development of different kinds of portable small devices,people put forward higher design requirements for chips which are widely used in these devices.Among them,low dropout regulators(LDOs)are widely used.For example,a complex and multifunctional chip may need more than ten LDOs.The performance requirements of LDOs are different in different application,but the overall design objective is to achieve low power consumption,low cost and high integration.At present,the capacitor-less LDO is a hot research area of LDO.Due to the removal of off chip capacitance,capacitor-less LDO is very suitable for circuit integration,which is in line with the developing trend of high integration.However,the stability problem will rise and the transient response of the capacitor-less LDO circuit will deteriorate with the decreasing quiescent current consumption.Nowadays,many scholars and engineers have carried out in-depth research on this problem,and also have given many solutions.According to these design requirements,a low-power fast-transient response capacitorless LDO is designed in this paper.This paper includes the following work.Firstly,the transient response performance of LDO is studied deeply,and five kinds of fast transient-response LDO structures are introduced,which provides guidance for the later circuit design.Secondly,the very low-power bandgap reference based on 55 nm CMOS technology was designed.It provided reference voltage for LDO circuit.All of the MOS transistors are working in the sub threshold region when the bandgap reference circuit enters the steady state.The simulation results show that the quiescent current of the whole bandgap reference is only 275 n A,the temperature coefficient is 40.2ppm / ?,and the output voltage is 1V.At the same time,a start-up circuit was designed to reduce the start-up time of the bandgap reference.With the start-up circuit,the start-up time is 8.9?s after the power on.Thirdly,the low-power fast-transient response capacitor-less LDO based on 55 nm CMOS technology was designed and applied to system on chip to meet the requirements of low-power,fast response and high stability.(1)Using the nest miller compensation technology to realize high stability of the capacitor-less LDO.(2)Using adaptively biasing technology to increase the loop bandwidth of LDO and improve the transient response performance.(3)By limiting the minimum current of LDO power transistor,the stability of LDO using adaptively biasing structure at low load current is solved.Within the load current range of 0-100 m A,the capacitor-less LDO is very stable.(4)By combining transient enhancement circuit with limited minimum current of power transistor circuit,it not only improves the stability of LDO under low load current,but also reduces the overshoot of LDO.The final simulation results show that the LDO consumes 20?A current and the output voltage is 1V at the load current of 0m A when the input voltage is 1.4V.When the load current changes from 0m A to 100 m A in 1?s,the settle time is less than 3.02?s,the undershoot is 179 m V.When the load current changes from 100 m A to 0m A,the settle time is less than 1.10?s and the overshoot is 142 m V.In addition,the power supply rejection of LDO at low frequency is 71 d B,the line regulation is 0.22 m V/V and the load regulation is 2.43?V/m A at the load current of 100 m A.