Research On Radiation Hardened By Design Of CMOS Integrated Circuits SRAM Memory Cell

With the rapid development of the integrated circuit industry,the proportion of memory in integrated circuits has reached 90%,and the large-scale application of memory has attracted more and more attention.However,as semiconductor devices become smaller and smaller,especially after entering the nanometer size,the memory cell is more and more susceptible to high-energy radiation particles in the radiation environment and is more prone to soft errors,resulting in reduced reliability of the memory.Static random access memory has been widely used due to its high speed and small area overhead.However,after the size is sharply reduced,the power supply voltage is continuously reduced,the operating frequency is increased,the SRAM memory cell is more sensitive to high-energy radiation particles,and the phenomenon of single event upset of internal nodes is increasing.At the same time,because the physical distance of the memory cell nodes is reduced,single particle incidence may cause multiple nodes inside the memory cell to be upset due to charge sharing,The most typical one is double node upset,which has become an important factor affecting memory reliability.The emergence of the double node upset problem puts new demands on the design of radiation hardened memory.In this dissertation,the concept of single-event effect,the generation mechanism and simulation modeling analysis are analyzed in detail for the problem of reliability reduction of SRAM memory cells.It is introduced that in the case of decreasing device size,SRAM memory cell will cause double node upset due to charge sharing effect.Then,for the reliability reduction of the memory cell,different levels of harden design methods are introduced.The basic knowledge of the composition,classification and evaluation index of SRAM is systematically summarized,and the data read and write simulation of SRAM circuit and the modeling methods of measuring key parameters such as noise margin and access time are given.Finally,this dissertation introduces the existing radiation hardened memory cells design at home and abroad,expounds the advantages and disadvantages of different memory cells.And proposes a problem that the existing partially hardened memory cells are difficult to be compatible with reliability,stability and access speed.A new radiation hardenened memory cell RHM-NS 12 T consisting of 12 transistors is proposed.The RHM-NS 12 T memory cell is a radiation hardened 12 T memory cell composed of 4 PMOS transistors and 8 NMOS transistors,and the internal 4 NMOSs form a stacked structure to reduce the power consumption of the memory cells,which avoids negative transient pulses generated by storage nodes based on upset physical mechanism,the negative feedback introduced between storage nodes effectively hinders the memory cell upset.Extensive simulation results show that the proposed memory cell can not only fully tolerate the upset of sensitive nodes,but also partially tolerate the double node upset caused by charge sharing.Compared with other memory cells,the power consumption,area overhead,read time and write time of the proposed memory cell are reduced by 18.28%,13.18%,5.76% and 22.68% on average,and the minimum noise margin reached 350.29 mV,the results show that the proposed memory cell make better tradeoff among area overhead,access time,power consumption and stability.