The Research On Radiation Hardened Technology Of Digital Integrated Circuits In Nanoscale Technologies

The integrated circuit industry is the core of the information industry, and it is also the strategic industry of the country. With the development of semiconductor technology, the performance of integrated circuits has been improved, but the reliability of the integrated circuit has become more and more serious. The feature size of integrated circuit continuously decreasing and the critical charge continuously reducing, while the occurrence rate of soft errors dramatically increasing with reliability facing severe challenges. At present, integrated circuit is entering nanometer era, and integrated circuit design for soft errors hardened becomes more and more important.This dissertation aims to soft errors of digital integrated circuits in nanometer technologies. We proposed effective hardened design based on research of existing design for radiation hardened latch. The framework of this dissertation as follows:This dissertation has carried out analysis of reliability problem of digital integrated circuits within nanometer technologies which indicated that soft error resulted from Single Event Upset is the main factor threatening reliable operation of integrated circuit. We elaborate basic conceptions of soft errors in the integrated circuit. The Single Event Upset mechanism and transient fault model are also introduced in depth. The radiation hardened technology of Single Event Upset was summarized. The circuit structure and working principle of hardening latch are analyzed.Based on analyzing the existing hardening latch designs, we proposed LCHL latch and STHTI latch. The LCHL latch employs a clocked CWSP cell at output stage to tolerate internal nodes transient fault. Meanwhile, a CWSP cell is employed at feedback loop of output node, to tolerate the negative effect of transient fault. LCHL latch has a good performance for radiation hardening. This latch realizes single event upset tolerant for all circuit node. And LCHL latch has lower cost than these existing hardening latches. The simulation results of HSPICE suggest that compared to FERST latch, SEUI latch, HLR latch, Iso-DICE latch, the proposed LCHL latch achieves 23.20% area reduction on average,55.14% delay reduction on average,42.62% power reduction on average, and 66.28% PDP reduction on average. The proposed LCHL latch achieves stable performance under PVT variations.The STHTI latch employs CWSP cell which has the filtering function to compose triple interlock. At the end of latch, the CWSP cell is also exploited to tolerate single event multiple upset. The simulation results of HSPICE suggest that compared to TMR latch and DNCS-SEU latch, the power delay product of the proposed STHTI latch was reduced by 58.93% and 41.56% respectively. Meanwhile, the proposed STHTI latch has less sensitiveness to process variations and better performance of noise resistance.LCHL latch and STHTI latch we proposed have a low cost and a good hardening performance for Single Event Upset. It’s helpful for improving the reliability of the integrated circuit and relieving soft error of digital integrated circuits in nanometer technologies.