Readout Electronics System Of The MIMOSA 28 Chip For The MAPS Detector

Monolithic Active Pixel Sensor(MAPS)is one of the best-developed monolithic pixel sensors with high position resolution and count rate capability.It has wide range of applications in high-energy physics experiments and astrophysics,the design of suitable readout systems for this series of detectors,is a key step in fulfilling these applications.The MIMOSA 28 chip is based on CMOS's Very Large Scale Integrated Circuit process and is designed using a new silicon detector technology that integrates detector elements and processing electronics on the same substrate.Based on MIMOSA 28 chip,this paper presents a kind of low-cost,high-speed and scalable readout system for MAPS series detectors,and designs the circuit and firmware for the readout system,develops the corresponding software system.The hardware part of the readout system is mainly divided into three parts:VC_BOARD acquisition board,LU_BOARD protection board and HPDAQmini Main-control board.The VC_BOARD acquisition board is equipped with MIMOSA 28 detector to complete the detection of charged particles,data acquisition,and·transmit the collected information to the back-end HPDAQmini Main-control board through the readout channel;LU_BOARD protection board has a variety of AD chips that monitors the current and voltage of the VC_BOARD acquisition board,and also controls the power supply of the VC_BOARD acquisition board to protect it.The HPDAQmini Main-control board has an onboard FPGA chip that completes command control,data storage and transmission control for the entire system,Main-control board leads 128 I/O ports through the FMC.The MIMOSA 28 chip control requires 18 I/O(10 configuration interfaces can be shared).Therefore,the system supports up to 14 MIMOSA 28 chips.At the same time,two DDR3 SDRAM provide 51.2 Gbps of cache speed with a cache capacity of 4 Gb;the Main-control board Ethernet has a maximum transfer rate of 500 Mbps.The firmware part is designed with the JTAG controller for configuring the MIMOSA 28 internal registers.The VC_BOARD acquisition board collects the data and transmits it to the FPGA,and implements serial to parallel,decoding operation in the FPGA,The MIG IP core provided by Xilinx is used to control DDR3 for data caching,and the Ethernet controller is implemented by FPGA to control command and data transmission.The software part mainly realizes the configuration of each hardware circuit through python script,write control software and analysis software,reads the required data from DDR3 memory and transmits it to PC for offline analysis through Ethernet.Test of the readout system includes three parts:hardware circuit test,transmission path test and chip application test.The hardware circuit test mainly tests the power supply and the clock.The transmission path test mainly completes the GTX performance test,verifies its performance under the 1Gbps and 5Gbps channels,and the transmission data throughput of the whole system to 500Mbps.Finally,chip application test is implemented.We have used MIMOSA 28 chip to test the whole readout system.Without using DDR3 cache,it can support single chip maximum data volume(320Mbps)readout.At the same time,under the condition of laboratory X-ray,we tested the simultaneous readout of two chips.The two chips are read out at the same time,and the data transmission is normal and error-free.According to the theoretical analysis,under normal conditions(single chip data throughput is less than 100Mbps),the system can meet the requirement of simultaneous readout of at least 5 MIMOSA 28 chips.