An FPGA implementation of a C4FM software-defined radio with Ethernet and JTAG interface

One target for research and development, software defined radio (SDR), reduces the cost of ongoing revisions and improvements to communications technology. SDR depends on the features of reconfigurable computing devices such as field programmable gate arrays (FPGAs). Tools and techniques are required to develop efficient FPGA based SDRs. This thesis examines the use of Ethernet and JTAG in SDR, and a continuous 4-level frequency modulation (C4FM) FPGA solution. A simple user datagram protocol implementation is used to provide a data bridge between the FPGA and workstation. Applications of the Ethernet system are discussed such as measuring bit-error rate, signal generation, and synchronous signal capturing. Along with the C4FM implementation, resource saving techniques are demonstrated for symmetrical FIR filters and moving averages. An innovative application of JTAG is discussed along with the tools developed to make it possible.