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The Design Of DDR3 Digital Video Buffer And Transmission System

Posted on:2018-01-03Degree:MasterType:Thesis
Country:ChinaCandidate:X J WangFull Text:PDF
GTID:2348330542951199Subject:Instrumentation engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of communication technology and computer technology,digital video transmission system plays an increasingly important role in modern national social production,digital video transmission system has been widely used in the fields of banking,shopping malls,traffic management etc..Especially with the rapid development of semiconductor technology,the transmission speed,transmission distance and storage capacity of digital video transmission system have been greatly improved,The design of optical fiber transmission technology,digital technology,network technology is combined to build a cascade DDR3 cache and digital video transmission system based on FPGA,the system is divided into video data sending and receiving video data.Howell company system using OV5640 as image sensor,using SFP module as the optical transceiver module,the use of XILINX,a new generation of high-speed FPGA device ARTIX7 100T?XC7A100T2FGG484I?as the main control chip to complete the design of the data transmitting end.In the data receiving end,in order to solve the problem of optical fiber data transmission and Ethernet transmission speed does not match the problem,using magnesium company?MT41J256M16HA 4Gb?memory chip DDR3 cascade storage space and speed improve the data cache.The use of Gigabit Ethernet interface,RTL8211 EG will cache data sent to the PC side,so as to achieve the data from the fiber side to the PC side data transmission,interface conversion,speed matching.The system uses Verilog to design video data frame module,video data analysis module,image data capture module,DDR3 read / write control module and UDP data transceiver module.High speed data transceiver core generated using XILINX's new generation Vivado development tools?GTP?and optical data transceiver module SFP data exchange,to achieve control of the DDR3 to read and write the call DDR3 Gigabit Ethernet MAC controller,IP Core using XILINX's solution,the data link layer and physical layer.In the system software design is completed,the use of simulation platform and Modelsim Vivado with the timing simulation and functional simulation of each module,debugging and verification of each module and the overall system after the completion of the hardware assembly.The experimental results show that the transmission system can transmit the video data of 720 P and frame frequency 30 fps RGB565 to the PC terminal stably and reliably,and the system runs well.
Keywords/Search Tags:Video data Transmission, DDR3, Video Data Storage, SFP, Gigabit Ethernet
PDF Full Text Request
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