Digital Readout Design And Implementation Of The MIC4 Prototype For The CEPC Vertex Detector

Since the discovery of the Higgs boson,the precise measurement of the properties of Higgs and the exploration of new physics beyond the Standard Model(SM)have been a hotspot in the high-energy physics.In order to accurately measure the characteristics of the Higgs particle,Chinese scientists have proposed the Circular Electron Positron Collider(CEPC)program.The Monolithic Active Pixel Sensors(MAPS),acts as the core component of the CEPC vertex detector,is used to measure the position and time information of heavy-flavour quarks and lepton.It requires high spatial resolution,fast readout,low power consumption,radiation tolerance,low material budget and other characteristics.The digital readout circuit design of a small size,which can read all the pixel position information independently without a loss,is one of the keys of the MAPS design.This thesis proposes a data-driven readout architecture combining the classical Token structure with the AERD structure,and realize the digital readout of MAPS in the CEPC vertex detector using Tower Jazz 180nm CIS process.The specific research contents and innovations are as follows:1.A new data-driven readout architecture,which Combining the Token with the AERD structure,is proposed:the Token structure is used in Super Pixel composed of 64 pixels in 8 rows and 8 columns,and the AERD structure is applied in Super Pixel array.The Token structure is used in the Super Pixel to achieve non-zero data compression and area reduction.The Super Pixel external AERD realizes fast readout and low power consumption of the 16 rowx8 column super pixel array.The results show that the super pixel area can be reduced to 25?m×25?m with Token technology,thus improving the position resolution.2.Design a digital readout circuit with no on-chip memory and real-time output data:a small FIFO is used in the MAPS chip to convert 23-bit data read by transferring the pixel array into 8-bit data firstly,and then framing the 8-bit data to output.Thus enables 8-bit parallel a real-time readout of MAPS and reduces chip area,which requires only 0.425?s per frame.3.The Back-end design and test of the digital readout circuit:According to the vertex detector design index,the timing of the digital readout circuit is constrained and the gate-level netlist is generated by Design Compiler,and then the layout design of the netlist is completed by Encounter.A good imaging effect is observed by testing the digital readout of the MAPS chip,therefore verifying the correctness of the digital readout design.