Research On Key Circuit Design And Test System Of Large Capacity Resistive Random Access Memory

In recent years,the rapid rise of big data,Internet of Things,and artificial intelligence has put forward higher requirements for data storage.However,the development of traditional non-volatile memory such as Flash has encountered obstacles when the semiconductor process nodes reach 22nm.So both academic and industrial communities began to explore the new generation of memory.As a member of new non-volatile memory,the resistive random access memory(RRAM)has become a research hotspot because of its high reliability,fast transition speed,small cell feature size and convenience of three-dimensional integration.This paper studies the resistance mechanism,structure of memory cell and sense amplifier revolving around the 64Mb RRAM project.The main contents are as follows.Firstly,by comparing the structural characteristics of 0T1R,1T1R,1D1R and other cell structures,the cell structure used in 64Mb RRAM is determined to be 1T1R.The layout of the memory cell is completed according to the 1T1R cell schematic,and then the memory cell is extended to the memory array.In this paper,64Mb RRAM is designed by segmentation array and hierarchical decoding.The memory array is divided into 4×39 small arrays.Each small array includes 2048×256 cells.In addition,each small array has its corresponding reference array.The reference array is used to provide a reference resistor access to the sense amplifier.Secondly,according to the readout characteristics of RRAM,a voltage-type cross-coupling sense amplifier has been designed in this paper.The pre-simulation results show that the sense amplifier can precisely read the data within 25 ns.The layout of the sense amplifier has been designed on the basis of the pre-simulation,and the performance is ensured by using the interdigital structure,the symmetrical design and the addition of dummy.The final layout area is 21.08×15.16 ?m2.After that the parasitic extraction and post-simulation work are performed,the post-simulation results prove that the sense amplifier circuit satisfies the readout requirements of RRAM.Finally,for the later test of 64Mb RRAM chip,this paper designed a 64Mb RRAM test system according to the working sequence and test requirements of RRAM.This paper also built the simulation verification platform,wrote the test vector and RRAM model,and the function of the RRAM test system was verified by using the modelsim software.By analyzing the simulation waveforms of reading,writing and different working modes,it was concluded that the RRAM test system designed in this paper can be used for the later testing of 64Mb RRAM chip.