Study On The Failure Mechanism Of The Resistive Random Access Memory (ReRAM) In1T1R Architecture

When the traditional memory devices have faced their physical limit, the researchers have developednon-volatile memories with novolstorage mechanismto replace the Flash memory. Among the new memories, the resistance random access memory (ReRAM) is considered as the most potential candidate for its simple MIM structure; perfectly compatible preparation process with conventional CMOS technology, extremely small area for cross-array structure, and the obvious advantages in high-density storage. However, to realize the promisingapplication of ReRAM, explicit switching mechanism and excellent reliability are required. Currently, the research of ReRAM is mostly focus on mechanism analysis and reliability development. In recent years, the research groups concentrated to investigate the memory machinasim of ReRAM, as well as devolope the reliability of the device.It’s really meaningful to clarify ReRAM data retention failure mechanisms, which would help to improve the property and lifetime of the devices, then to promote the practical application of ReRAM.In this paper, we adopted the1Kb1T1R array as the research object to study the reliability of ReRAM. The main work includes analyzing the reliability problems arising from1T1R architecture, researching the data retention characteristics, and exploring the failure mechanism.Firstly, we fabricated1Kb ReRAM1T1R array in our laboratory. The transistor was fabricated by standard0.13μm logic process and the ReRAM device with Cu/HfOx/Pt structure is integrated on it. The ReRAM celland bitline were patterned by liftoff process. The1T1R ReRAM array was finished when the bit lines are connected with the column decoder by metal.Secondly, we studied the reliability problems in1T1R architecture, including the impact on the forming successful ratio and the restrictions of multilevel storage. Throughin-situ monitoring the voltage drop on ReRAM cell,it’s obviously that the gate bias should overcome not only the voltage potential aroused by source bias but also the increased threshold voltage (V’Th) by body effect in1T1R architecture during forming/set process. TheVRRAM would keep nearly constant when IR=IDS, which causes programming failed,thenthe ReRAM array programming successful ratio is affected. Due to the limitations of gate bias, ReRAM will not beproperly switched and the ability of ReRAM multilevel storage will be limited.Thirdly, unlike previous experimental methods, we analyzed the data retention properties of ReRAM by statistical methods utilizing the1Kb ReRAM array. From theobservations of HRS/LRS retention characteristics under different cycles, a physical model based on copper diffusion was developed. Considering the probability of Cu ion jumping out of filament is inversely proportional to the Cu concentration in the oxide and the active energy (Ea) for Cu moving. The LRS retention is improved after the cycling as a result of the lowered jumping probability of Cu out of the filament, while the HRS retention is degraded after the cycling because of the reduced tunneling gap.Finally, the retention characteristics of HRS/LRS can be significant improved by current program mode. For the same effective CF area, single filament generated under current program method, is helpful for better LRS retention as the diffusion speed of Cu is decreased. On the other hand, the HRS as well as the tunnel gap legthen was generally increased, resulting in better HRS retention. The current program method is an effective way to develop both HRS and LRS retentions.