Design Of Peripherals Critical Circuit Based On Bipolar Resistive Random Access Memory(RRAM)

With the development of technology,the subjects of artificial intelligence,big data,could computing and internet of things are getting more and more attention.These disciplines are all based on the collection and analysis of data.Besides,the information shows exqonential growth with the development of science and technology and the improvement of people's consumption level.Higher resolution photos and videos require more storage space.And with the growing demand for low-power and high-performance memory,the non-volatile memory consumer market has been boosted.Flash memory occupies a dominant position in the current nonvolatile memory market,but as technology advances and people's needs increase,flash memory encounters bottlenecks in terms of storage data density,power consumption,and read and write speeds.People are constantly looking to explore emerging storage technologies and materials to solve these problems.One of the promising candidates in the next generation is the resistive random access memory(RRAM)because of superior characteristics including high storage density,low power consumption,simple structure and compatibility with standard CMOS process.However,due to the fact its mechanism is not completely clear,it is necessary to design a suitable peripheral circuit and a programming algorithm according to the behavior characteristics of resistance change.In this dissertation,we show the advantages of RRAM by comparing with the mainstream of new types of memory and exploring its storage mechanism.To solve the problem that the RRAM device model for the simulation,a circuit model of the RRAM device based on MOS transistors and another model based on Verilog-A are respectively established according to the electrical characteristics of the RRAM,Also,the accuracy of the model is verified by simulation.Secondly,we analyzed the structure of common RRAM cells and determined the structure of memory cells using 1T1R.And based on 1T1R memory cell structure,we design a highly reliable read and write scheme.More,the common programming algorithms are analyzed and a programming algorithm with adjustable pulse width and pulse height is designed and simulated.Then,the optimization and simulation of the peripheral critical circuits including the sense amplifier and decoding circuit are given.Finally,we verified the integrity of the chip's read and write functions.