Study On Sense Amplifier Ciruit Design Of Ferroelectric Memory

As an important part of integrated circuits,memory has always been an important object for circuit designers.With the development of integrated circuits and the continuous improvement of various new technologies,the requirements for memory development have also increased rapidly,so the research on new types of memory is becoming more and more urgent.Driven by social needs,various new types of memory have also been developed,such as ferroelectric RAM,magnetoresistive RAM,and resistive RAM.In foreign countries,the development of these memories has been relatively mature,but domestic research is still improving.As a new favorite in memory,FRAM has naturally become an important research object.The performance of ferroelectric memory is mainly reflected in the fast reading and writing speed and long service life.The data read time of the ferroelectric memory refers to the total time consumed from the effective input of the address signal to the effective output of the data.The most effective way to increase the read speed of the ferroelectric memory is to improve the design of the sense amplifier in order to improve the signal amplification efficiency.The service life of a ferroelectric memory is mainly determined by ferroelectric materials,but after a large number of repeated use,ferroelectric materials will fatigue,resulting in weakening of ferroelectric characteristics,which will affect the service life of the ferroelectric memory,which is mainly reflected by the sense amplifier the recognized window voltage becomes smaller.Therefore,the key factor for improving the performance of ferroelectric memory is the performance of the sense amplifier,so the research on the sense amplifier of the ferroelectric memory has important significance.Based on the significance of this research,this paper focuses on the key factors that need to be considered in the design of ferroelectric memory sense amplifiers,and proposes an effective sense amplifier design.Under the premise of using a latching sense amplifier as a basic amplifier,a pre-amplification function is realized by adding a first-stage cross-coupled pull-up transistor.Under the pre-amplification effect,the small voltage difference on the bit line can be amplified to nearly half the power supply voltage difference.This can effectively avoid the negative effects caused by mismatch of the sense amplifier and improve the service life of the ferroelectric memory.Becausethe first-level amplification process is added,the amplification delay is increased to a certain extent.However,by sacrificing the time consumption of the amplification,the accuracy of the amplification process and the life of the ferroelectric memory are increased.On this basis,a ferroelectric array architecture that can save sense amplifier resources is also proposed.The sensitive amplifier designed in this paper uses Huahong Grace 0.13?m process,and the simulation tool is mainly hspiceD simulator of CadenceIC616.The simulates the reduction of the bit line voltage difference caused by the fatigue of the ferroelectric memory cell and the offset voltage caused by the mismatch of the sense amplifier devices.The simulation results show that the sensitive amplifier designed in this paper can effectively avoid the negative effects caused by offset voltage and delay the time when the bit line step difference is reduced due to the delay of the ferroelectric memory cell fatigue.To some extent,the yield of the sense amplifier and the service life of the ferroelectric memory are increased.