Research And Design Of Adaptive Phase-Locked Loop Based On 28nm CMOS Technology

As the mobile communication network gradually enters the era of 5G network,higher bandwidth and data transmission rate require the chip to have a wider input frequency range and faster working speed.As a clock generation module of the chip,the traditional phase-locked loop?Phase Locked Loop,PLL?has a narrow input frequency range and a fixed loop bandwidth,which is difficult to meet the requirements of various communication protocols.The proliferation of smart devices has driven the diversification of chip applications,requiring the design of better-performing PLLs to meet the increased demand for system clocks from a wide variety of smart chips.This work presents an adaptive PLL that allows the loop to generate constant loop dynamics that are proportional to the reference frequency and that are almost independent of the division value,output frequency,process,voltage and temperature?PVT?.By introducing the background of PLL research,the working principle and classification of PLL are briefly introduced.The traditional PLL and charge pump phase-locked loop?CPPLL?are analyzed layer by layer.The significance of adaptive PLL is revealed and the working principle of adaptive PLL is described.According to the application requirements of the adaptive PLL,the performance index of the designed adaptive PLL is determined,and the loop parameters of the PLL are designed according to the performance index.This work focuses on the design of the bias generation circuit,the startup circuit and the high-speed programmable prescaler.The innovative work on adaptive PLL design is reflected in:?1?For ultra-deep sub-micron,such as the 28-nm process,the reduction in process size makes transistor parameters sensitive to process variations and size mismatches,which may cause adjacent delay cells of conventional ring-controlled VCOs to have different amplification factors,resulting in the noise of the loop cannot be amplified and the oscillator does not self-oscillate.This work designed a bias generation circuit to provide the VCO with the appropriate bias voltage.By introducing the interference required for loop start when the control voltage V_ctrltrl drops to a certain value,the reliability of the oscillation start of the VCO is improved.Using the Monte-Carlo simulation,the VCO was subjected to 50 sampling statistics on the process parameters.The simulation results show that the VCO can reliably oscillate.?2?The legacy PLL turns on the loop when the VCO is started,which providing a longer pre-start time for the PLL.This work presents a startup circuit,setting V_ctrltrl to a specific value in a controllable period of time by presets the control voltage V_ctrl.The output signal of the VCO is calculated after the VCO is started.When the count is full,in other words,when the VCO is stably started,the indication signal is output to the phase frequency detector?PFD?,and then the PLL loop is turned on.The function of the startup circuit is verified by simulation,and the result shows that the startup circuit can shorten the PLL pre-start time and shorten the lock time of the PLL.?3?For the range of the conventional frequency divider is limited,the frequency division value is not programmable,and the frequency division speed is slow.This work designed an high-speed programmable prescaler to achieve ultra-high-speed frequency division by quickly presetting the state of the latch node of the internal frequency divider module to avoid register setup time violation caused by excessive input clock frequency.Wide programming range with division values from 2 to 2^N.The simulation proves that the high-speed programmable prescaler has an input clock frequency of up to 10 GHz and a frequency division range of 2 to 2⁸.The design uses Global Foundry's 28nm CMOS process,the power supply voltage is 1V,and the circuit is simulated by Spectre.The simulation results show that when the input frequency range is within 25⁴00MHz,the loop bandwidth of the adaptive PLL changes with the reference frequency,and the loop remains constant;VCO output frequency range is 1⁶GHz;the high-speed programmable prescaler has a frequency range of 2²⁸;adaptive PLL power consumption is less than 20mW;lock time is less than 6?s.The results demonstrate that the designed adaptive PLL can meet the design specifications.