.0.18 Um Design, Low-power Serial Eeprom Ip

This thesis presents the study of non-volatile memory,specially the studying about the EEPROM cell.An ultra low-power consumption 256×8bits embedded EEPROM is designed and implemented in HHNEC 0.18urn EEPROM technology. In this thesis,detailed analysis on the sources of main costs and the relevant low-power design methods are described.A proper charge pump circuit and a novel clamping circuit are designed to optimize programming power consumption.An important read out circuit that consists of the read out timing control circuit,SA (sense amplifier) and an output latch,is described particularly to optimize the read consumption.For a power supply of 1.8V,the typical average current of 174uA and 31uA for programming operation and read operation,respectively,can be achieved at read frequency of 5MHz.