Resrech On A Serial EEPROM Test Method With Near Field Communication

As one of the most widely used memories today,EEPROM(Electrically Erasable Programmable Read Only Memory)is widely used in integrated circuits due to its loss of data after power-down.Currently,as semiconductor processes continue to evolve,the demand for memory performance continues to increase.In order to ensure that the functions of the memory at the beginning of the design can be fully presented,its test methodology has become an important research goal of many integrated circuit workers.In recent years,the research progress in EEPROM testing mainly focuses on the following aspects:(1)How to solve the problems faced by the chip in test time,test difficulty and random error.(2)Test implementation of RF parameters for EEPROM with NFC(Near Field Communication)function.(3)How to find a more cost-effective mass production test solution for the chip in the current low-cost background of IC testing.This paper aims at the test life cycle of a near field communication serial EEPROM,builds the overall test plan,designs the test platform,researches and optimizes the test flow,and proposes a new method for test data analysis.The main research work is reflected in:1.For the problem of high failure rate of some test items after the Trim test process,we studied the cause and distribution law of the failure items,used the number of adjustments to increase the key parameters,and the test time with the increase of the test time.Control,proposed an optimization method for the overall repair process,and improved the yield of test items.2.In view of the currently expensive NFC function mass production implementation on the market,we studied the ISO/IEC 14443 Class A protocol followed by the chip and the internal programming functions of the existing ATE.Using reasonable timing settings and test program writing,a scheme for realizing the NFC function between the chip and the chip is proposed by the ordinary digital logic type ATE.Avoiding the purchase of RF-specific ATE or other RF upgrade components,reducing the cost of testing the chip while maintaining mass production testing.3.In view of the non-connected output voltage interference problem of the chip,we study the root cause of the chip and propose a modification scheme based on the probe card.The feasibility of the implementation of the scheme was verified by the test results of the new needle card sample,and the non-connected output voltage between adjacent stations was obtained.In view of the fact that the near-field communication echo waveform is not obvious,we studied the matching circuit and started the simulation analysis.The proposed optimization scheme provides a transformation direction for the same type of EEPROM test.4.For the large amount of data generated by the chip after the sample test,we use statistical methods for analysis.Based on the original test yield,test pattern and test time,data analysis methods such as test full coverage,normal distribution,multi-station single chip and class A uncertainty are proposed to ensure the reliability of test data.Based on the test method and process proposed by the above research,an EEPROM product has completed the CP test,and will be widely used in the cold chain and electronic shelf label field in the future.At the same time,the test yield of the product is more than 95%,which is close to the standard of mature test scheme in the industry.