Design And Implementation Of Data Recording Device Based On SRIO

With various high-pixel,high-frequency frame imaging devices widely used in the aerospace industry,imaging devices need to transmit and process image data at a higher rate in a short period of time.Therefore,high-speed data transmission and reliable storage are the main research contents of data recording devices.In response to this problem,this paper aims to design a data recording device that can realize high-speed data transmission and reliable storage.Firstly,in order to achieve high-speed transmission of 2.5Gbps,this paper adopts SRIO transmission protocol,designs SRIO interface circuit,realizes high-speed data transmission by SRIO IP core.And through the DDR logic control unit to achieve high-speed transmission and low-speed storage data interaction.Then,in order to verify the correctness of the SRIO IP core setting,through the closed loop self-test and using the simulation software to perform timing simulation.Secondly,in order to realize the LVDS transmission of 100 meters,the LVDS interface circuit is designed.At the same time,the combination of invalid number and effective number is designed for the disadvantage of unstable LVDS transmission link in random synchronous mode,which greatly improves the stability of the link.Finally,in terms of data storage,the traditional one-check operation and the RAM-based Flash inherent invalid block management method takes a long time and consumes a large amount of resources.A management method based on the integrated block is designed to shorten the invalid block detection time to 25%.At the same time,in order to solve the problem that the traditional burst invalid block management method is not suitable for high-speed transmission and occupying large internal resources of the FPGA,an idle readback is further designed based on the integrated block management method.In addition,in order to improve the memory write speed,an alternate double-plane page programming pipeline isused;Considering the problem that the memory read rate is reduced due to the introduction of the ECC check code during memory read and write,a double buffer alternate reading method is designed to improve the memory read rate.Through the establishment of the corresponding software and hardware test platform,the data recording device function and performance indicators are fully tested.After extensive testing,the device can achieve 2.5Gbps high-speed transmission,100 m LVDS transmission and reliable storage of data.