Effects Of Single-event-induced Charge Sharing In 90 Nm Bulk Cmos Technologies

In radiation environment when high energy ion strikes at semiconductor material charge will deposit along its track and charge sharing effect will occur if multiple sensitive nodes collect the charge. Due to Complementary Metal Oxide Semiconductor (CMOS) scaling trend, charge sharing has been a more and more significant issue of Single Event Effects (SEEs). Charge sharing can trigger Multiple Bit Upset (MBU) and Multiple Node Upset (MNU), which has been a serious problem about reliability in nanometer technologies.In present semiconductor technology, the main physical mechanism of charge sharing has not clearly been found. And there are still intractable difficulties in modeling and hardening of charge sharing. Moreover, the impacts of technology parameters such as concentration and the arrangements of device layout have not been studied. In this thesis, we thoroughly study the influence of P~+ deep well doping concentration, the depth of STI and the arrangements of device layout on charge sharing in order to explain the physical mechanisms of the effects of these parameters on charge sharing and find an effective method of restraining charge sharing, based on 90nm CMOS dual-well technology. The main work and contributions of the thesis are as follows:(1) Using TCAD simulation, it is concluded that under 90nm CMOS dual-well technology, doping concentration in P~+ deep well has a more significant effect on charge sharing in PMOS than that in NMOS. The main reason is that increasing doping concentration of P~+ deep well can make the disturbance of the potential in N-well become smaller, which will reduce the bipolar effect of passive PMOS; but the potential in P-well changes little.(2) By changing the depth of STI, we have simulated the impact of STI on charge sharing and compared the differences of charge sharing between NMOS and PMOS. TCAD simulation results show that increasing STI can restrain charge sharing of NMOS effectively, and 550nm is the effective depth for the prevention of charge diffusion, beyond which the collected charge almost keeps constant; for PMOS, charge sharing decreases linearly with the increment of STI depth.(3) Charge sharing of different layouts between two devices is investigated. TCAD simulation results show: for NMOS, the closer passive drain is to the location of heavy ion strike, the more serious the charge sharing is; but it is worse for PMOS that the passive source is placed nearer to the location of heavy ion strike.Finally we forecast the research area of charge sharing in the future.