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Research And Implementation Of High Speed Data Acquisition System Based On Optimized LMS In FPGA

Posted on:2020-10-29Degree:MasterType:Thesis
Country:ChinaCandidate:J N DingFull Text:PDF
GTID:2428330572972926Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
At present,with the rapid development of information technology,the collection and processing of various data has become an indispensable part of modern industrial control and scientific research.The data acquisition system is the bridge between the intelligent instrument and the external physical world.High-speed data acquisition and real-time transmission is always an important research direction of data acquisition system.Therefore,the emergence of FPGA technology provides a new solution for this.FPGA is a hardware programmable device.With the rapid development of the technology of FPGA,the functions of CPU and DSP are gradually integrated.FPGA can not only solve the problems of miniaturization,low power consumption and high reliability of electronic system,but also become very complex with the continuous improvement and enhancement of its functions.This paper introduces the principle of high-speed acquisition analysis and the implementation of adaptive filtering,the implementation of each module on FPGA hardware is studied.The acquisition speed can be improved by using FPGA,and the accuracy can be improved by using LMS(minimum mean square error)algorithm.When the LMS algorithm is implemented on hardware,the hardware implementation brings the bottleneck of computation and limits the iteration speed.Although the proposed delay LMS algorithm has some effect,the existing delay information has a bad influence on the convergence performance of the algorithm.To overcome these shortcomings,a constraint parallel delay LMS algorithm is proposed to improve the convergence performance of the algorithm and increase the computational complexity.Constraint parallel delay LMS algorithm is a kind of improved LMS algorithm which combines delay and parallel technology.Under the same conditions,this algorithm has smaller step size limitation,faster convergence speed and higher data throughput than the delayed LMS algorithm,while maintaining the efficient and simple implementation of the delayed LMS algorithm.It provides a new solution for the development of high-speed information acquisition.
Keywords/Search Tags:High-speed data collection, FPGA, Improved LMS
PDF Full Text Request
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