The FPGA Design & Implementation Of The Data Exchange Technology Of High-speed Adc

Research on key technologies of data exchange with the Ethernet protocol PCIe bus speed data acquisition card based on the center of this article.When the sampling clock circuit design, we use a frequency synthesizer chip and clock distribution chips get sampled signal, then the use of two parallel ADC chip differential sampling approach. The main chip of choice, we used the Xilinx Virtex-5 Series FPGA chip, using VHDL language for each module-level design. We use the PCIe bus and Ethernet protocol is based on UDP / IP protocol to communicate with the PC data acquisition card. In PCIe module program selection, we have adopted a moderate cost, the workload is small and does not require the IP system resources hardcore, then the design of the user interface, designed to receive, transmit, control registers, and various sub- module, DMA read and write operations. The Ethernet protocol is selected path, in order to more efficient use of system resources and faster data communication. In the design UDP / IP module, we use a LUT approach, a more efficient implementation of the transport layer(UDP / IP module) and link layer(EMAC core) between the data communication, while, after the design of efficient nuclear EMAC, and the data communication between the implementation and realization of the transport layer data transmission and reception between the physical layer, and design a reasonable user queue module.Design a feasible after each module, but also functional simulation(Modelsim), comprehensive layout, logical analysis(ChipScope) and bandwidth test(Wireshark), etc., to verify the feasibility of the program topics. In cooperation with the responsible driven design and hardware interface design students successfully achieve high-speed data acquisition card design.