Multifunction PWM Core Design Based On APB Bus

PWM(Pulse Width Modulation)is a very effective technique for controlling analog circuits using digital signals.Its basic principle is to control other circuits by changing the period and duty cycle of PWM waves.PWM control technology is widely used in many fields such as communication,measurement,motor control,power control and power control.PWM control technology is the most widely used in inverter circuits,and is also the core of variable frequency technology.It also plays an important role in industrial control such as measurement and speed control.In recent years,with the rapid development of intelligent products such as intelligent robots and unmanned aerial vehicles,the application of motors,especially brushless DC motors,has become more and more widespread,and PWM control technology has become a major control technology for motor control.Field research hotspots.Therefore,it is very meaningful to study the PWM generator.SoC(system-on-chip)is a system that integrates many system-critical components on a single chip.The general So C system integrates components such as CPU cores,memories,buses,and peripherals,and can implement signal acquisition and conversion.Storage and processing.So C technology has become the darling of the IC design industry due to its many advantages such as low power consumption,small size,multiple functions,high speed,low cost,and short development cycle.Therefore,in order to comprehensively compare the implementation of PWM generators,this thesis designs an IP core that can generate PWM waves and capture the cycle and duty cycle of PWM waves based on So C technology using Verilog language,and names this multi-function PWM core circuit as ETM.(Enhanced Timer)core.This design is based on the AMBA2.0 APB bus and uses a top-down design approach.First,the APB bus protocol and the functions of the timers in the STM32 series chips were studied by consulting relevant data,and the functions,top-level interfaces,and module divisions of the ETM core were determined.Then,through the investigation of related circuits,the realization principles of frequency dividing circuit,capture PWM circuit,output PWM circuit,dead zone insertion circuit,and DMA transfer circuit were studied.Based on this,combined with the requirements of the internship project,Verilog was used separately.The language has designed the frequency dividing module,the register module,the input module,the counter module,the PWM generation module,the dead zone insertion module,the software forcing module and the output module.Then,the principle and method of functional verification,DC synthesis,LEC equivalence check and STA static timing analysis are studied.Based on this,the functional simulation of ETM core is performed using Ncverilog,and the logic synthesis is completed by Design Compiler,using Prime Time for static timing analysis,running LEC for equivalence checking.Finally,combined with the verification results,it shows that the designed ETM core satisfies the design requirements and finally achieves timing closure.This design follows the basic functions of a general-purpose timer and expands the function on this basis.In addition to the basic functions of capturing PWM waves and issuing PWM waves,some other functions are added.For example,the function of inserting a configurable dead time into the output signal is realized,and the function of input capturing the input waveform and transferring the data to the memory by using DMA is realized,and a certain number of pulses are automatically issued under the excitation of the external input.The function.The realization of these functions reflects the versatility of the ETM core.