Testing And Application Design Of JTAG Soft-core

Currently, the digital system is composed of a large amount of highly fine packeted ICs, such as PGAs, BGAs and so on. It could lead to narrower space between connections on the PCB and closer distance between test points, and it could even make some test points inaccessible. So, the traditional test methods based on probes or nails beds are no longer available. With the rapid development of electronics technology, great evolution happened on testing technology of Circuit Board, a new testing technique for interconnects among ICs on Printed Circuit Boards was invented in the later 20'h Centrury and applied in more and more fields. This newly developed techique is Boundary-scan Technique (BST), and it is described in IEEE-1149.1, which is also named JTAG Specification. JTAG urges the development of DFT(Design for Test) design,which can only save much expense and time on PCB design, but also can provide an effective and convenient way of "download" and "read" for the inner registers of chips.JTAG, that is IEEE 1149.1 standard, can realize the data transfer function only by five pins. It can only test all kinds of ICs and macro cells in the chips, but also can test responding PCBs. As a design for testing technology,the boundary-scan test fixes a special element called Boundary-scan Cell(BSC)between the device input pins and the core logic inputs,or between the core logic outputs and the device output pins.Thus,the BSC acts as the virtual test probe that carries out the test stimulus and captures the test respondences.According to deep research on JTAG, detailed method of realization for JTAG structure is presented, and design for JTAG chip is achieved.First,a RTL level module of JTAG soft-core based on Verilog is constructed, and then logic synthesis and layout design is achieved..The main job can be divided into the following parts:(1) Research on boundary-scan technology;(2) Construction and verification of JTAG verilog module;(3) Logic synthesis of JTAG soft-core;(4) Layout design of JTAG.The design result indicates that the whole test system works smoothly.The paper is characterized by being closely attached to IEEE1149.1 standard,and after analysis on JTAG instruction for the first time and also RTL level modeling and simulation of JTAG,we can conclue that the fundamental part in JTAG testing satisfys the design specification; and studies and discussions on design ideas and methods of the JTAG chip and also key technologies in ASIC design were done. The novel idea of the paper lies in the fact that the entire design cycle of JTAG chip is completely and clearly presented in the paper,which is of good value and guiding significance for design of other ASIC chips afterwords.