Design And Implementation Of High Speed Triple-DES Algorithm IP Core

With continuous enlargement of network size and rapid development of network technology, information security issues on network seem to be more and more serious.Among all the possible measures to solve this problem,encipherment would naturally be the best choice.To meet the need of security in broad-brand network of high speed,this paper aims at developing a high speed IP core of Triple-DES in ASIC.After a brief introduction of the symmetric block cipher algorithm-Triple-DES,this paper focuses on the design of the architecture of this IP core and the implementation of its main modules.In order to guarantee a high rate of encryption and decryption,we optimize the design from three aspects as following.First,all the iterations in the algorithm have been unrolled so that the IP core can be designed well in pipeline.The Triple-DES is namely computed by repeating in three times a single DES, which contains sixteen iteration rounds.Our design with twelve pipelined steps takes a clock cycle to perform its four rounds.Due to pipeline technology,64-bit plaintext blocks can be fed in one by one per cycle,and then the corresponding cipher-text blocks come out one by one every cycle after the first twelve clock cycles elapsed.So the clock frequency and the throughput of this system have been increased.Second,modules are designed in such a way that they can work in parallel,in other words, they are designed separately.In order to further improve the speed of this cipher chip,the function of encryption/decryption and sub-key generation of Triple-DES is implemented in a separate module respectively.All the sub-keys needed by Triple-DES are generated in parallel by sub-key generation module and then fed into the corresponding DES module through sub-key multiplexers for processing.Moreover,three DES modules can work in parallel too.As a result, the speed of the whole system in encryption or decryption can be dramatically improved. However,the gain of speed in this design comes at the cost of more hardware resources.Third,through analyzing and comparing the several candidates for implementing S-Box, which plays a critical role in designing the IP core,we implement it using ROM that is a firm IP core in FPGA and configured as LUTs.Owned much to it,less hardware resources are consumed and higher speed is achieved.This IP core is coded in VHDL and implemented in a Xilinx Virtex4 family FPGA device.The Design is synthesized and simulated using ISE8.2i.The result shows that our design can work well at 50MHz,with the rate of 3.2Gbps for encryption or decryption.Since this IP core is a soft one,it can be easily integrated into any high-speed broadband network security products or application server systems as a hardware encryption/ decryption module for reuse based on the requirements.