Research On Timing Closure Between Different Analysis Mode Based On Innovus

As the process of semiconductor gradually transferred from 28 nm to 16 nm or even 7nm,tapeout conditions between different areas of the same chip were different,resulted from timing uncertainty caused by on-chip variation.Process variables that were increasingly difficult to be controlled made the traditional static timing analysis methods with multiple process corners including process,voltage and temperature difficult to accurately estimate the impact of on-chip variation on timing analysis.At this point,accurate and efficient static timing analysis has become the key to ensure that the chip can work well.The influence of process variation in the current 28 nm process on the cell delay based on the analysis model of the timing lib was firstly analysized by this paper,OCV analysis mode was used to simulate the timing error caused by process variation.As the simulation of process variations with globally uniform derating factor in OCV had its shortcomings,a relatively accurate advanced OCV mode was presented to achieve a more practical purpose through the dynamic adjustment of the derate value.Due to etching,ion doping and other uncertainties in the 16 nm process environment,ions were randomly distributed in silicon,this proposed a new statistic-based SOCV mode,which was based on the statistical thinking of mean and sigma to simulate the process deviation and the probability of cell delay.Based on the timing analysis mode of OCV,AOCV and SOCV,Cadence tool Innovus combined with specific 28 nm and 16 nm GPU physical design block was used to study the effect of different analysis modes on timing closure in different stages of the back-end.Finally,a simple exploration of the SOCV improvement mode was conducted,compared with the default SOCV mode,and validated with Innovus.As the selection of timing arc and timing path was affected by the delay analysis of the multiple-input logic gate unit in the design,which also affected the convergence of timing,the impacts of the two different analysis methods based on GBA and PBA in OCV,AOCV and SOCV mode for timing analysis were explored and verified.Verification showed that the timing impact of process variation could be more fully simulated in OCV mode than that in the best-case worst-case traditional mode,and the derate value varied with the depth of the path was taken into account in AOCV mode,TNS in route stage was about 15.1% better than that in OCV mode.The SOCV mode at 16 nm was more accurate to simulate the random variations with on-chip variation,the route stage's TNS with setup was about 40.2% better than that in AOCV mode,the related reduction of the runtime was about 7.4%,which resulted in fast convergence of timing,verified that SOCV was the most ideal timing analysis mode in chip design under current 16 nm node.For the analysis of multi-input logic gate units,the verification showed that PBA was more accurate than GBA,while tool analysis time was relatively longer,in a result,PBA was generally used during sign-off stage to ensure that the timing before the final tapeout was more accurate,and GBA was mainly used in the early stage of design to shorten the cycle of timing analysis.