Research On Optimal Layout Floorplan And Placement Based On Innovus

In recent years,with the gradual evolution of integrated circuit process feature size to the deep nano level,the market also puts forward higher and more stringent requirements on the power consumption,performance and product design cycle of consumer electronics.In the traditional back-end physical implementation design process,floorplan,power plan and route,placement,clock tree synthesis,route,physical verification,sign-off have been adopted.However,with the advanced process reaching 7nm,5nm and the coming of 3nm node which will be fully deployed,the timing closure and power of the circuit will be reduced,and the difficulty of implementation is rising sharply.How to optimize the traditional backend physical implementation process to get better timing,lower power consumption,shorter line length,smaller congestion has become an urgent problem to be solved.Based on the specific project in the enterprise,this thesis studies a new layout planning and method based on innovus,the floorplan and routing EDA,and applies it to a module implemented using 28 nm process.It uses a new mixed placement methodology to carry out layout floorplan and placement of chip modules,mixed placement of macros,and standard cells placement.The main research work of this thesis is as follows:Firstly,the process steps and implementation methods of mixed placement are studied and determined,and compared with the traditional physical design process.According to the flow methodology of the two methods,and the traditional floorplan and mixed placement method placement of the target module are carried out respectively.The congestion evaluation and timing analysis are carried out before the clock tree synthesis of the two methods,and the quality of results index is compared.Then,the structure of clock tree and the selection of inserted clock buffer are studied.The clock tree synthesis,route and subsequent physical and timing verification are carried out.Secondly,in order to make the chip module reach the final sign off standard,the timing optimization and the number adjustment of clock buffers are carried out for the physical implementation of the mixed placement methodology,so as to reduce the delay of the clock tree and the clock offset as much as possible.Some of the default wire winding rules are set to prevent crosstalk.Some high frequency clock signals are shielded to ensure signal integrity.During the physical verification,the DRC and LVS of the module are checked and repaired to ensure that the module does not violate the design rules,and the electrical performance of the layout is consistent with the front-end netlist function.Finally,the timing,power and congestion degree of the two methods are compared in the key stages of layout,clock tree synthesis and routing.It is concluded that the chip module implemented by mixed placement method has absolute advantages in the comparison with quality of results indicators,and the advantages obtained by the comparison can be maintained in the clock tree synthesis,wiring and other stages,until the final sign off stage.The data processing and analysis results show that the timing convergence effect of the designed module is nearly 40 times better than that of the traditional method,the interconnect length is reduced by 10%,the power consumption is reduced by 7.4%,the degree of congestion is greatly relieved,and the physical design cycle is shortened by 28.9%.It shows that the mixed placement methodology is more efficient and competitive than the traditional methods in chip physical design.