Efficient and accurate statistical timing analysis for non-linear non-Gaussian variability with incremental attributes

For four decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. The principal categories of improvement trends are integration level, Cost, speed, power, compactness and functionality. Most of these trends have resulted principally from the industry's ability to exponentially decrease the minimum feature size used to fabricate integrated circuits. Of course, the most frequently cited trend is in integration level, which is usually expressed as Moore's Law (that is, the number of components per chip doubles every 24 months).;With the aggressive scaling of the recent technologies, process variability is growing. Dealing with variability has become an integral aspect of high performance digital integrated circuits and indispensable for first-time-right hardware and cutting-edge performance [1]. Mainly two reasons can be attributed to this trend. First, critical dimension of the circuit are scaling faster than our control on the manufacturing process, resulting in the proportionate increase in the variability of physical dimensions, such as the effective length of a transistor channel [2]. Second, atomic-scale randomness, e.g. variation in the number of dopant in the transistor channel, is increasing [3]. Under these conditions, it becomes essential for the design tools to account for the uncertainties and to design robust circuits that are optimized for the device parameter variations.;Traditional design automation techniques (corner based techniques ) are not capable of dealing with these fabrication variations. As a result, the design obtained may be sub-optimal or may not even satisfy the design constraints. Thus it becomes imperative to find new methods to handle the variations in the design flow which will be both accurate and fast. The objective is to develop techniques to create robust design that is not prone to the manufacturing variations and which helps in increasing the yield of the ICs.;In this work, we focus on the problem of timing analysis in the presence of fabrication variability. Generally, the timing analysis techniques which handle timing analysis in the presence of variability are called Statistical Static Timing Analysis due to obvious reasons. Unlike current approaches for non-linear, non-Gaussian SSTA [4] which have numerical components, our approach is completely analytical. We also investigate the incremental aspects of SSTA and present (1) a fast yet accurate incremental approach (2) a method to efficiently estimate the expected error injected by incremental SSTA, which can be used to decide when accurate SSTA should be executed and when incremental SSTA would suffice. Our approach (non-incremental) is about 9588 times faster than Monte Carlo whereas an existing state of the art non-linear, non-Gaussian SSTA engine [4] is only 31.3 times faster. Further, the Root Mean Square (RMS) error of both the approaches is comparable w.r.t. Monte Carlo. Our incremental approach is 23 times faster than the proposed accurate SSTA approach. Moreover, our error estimating methodology can accurately capture the trends of error injection due to incremental SSTA.