Research On Timing Optimization And Timing Clourse Based On SOC

With the development of integrated circuits,chip feature size is getting smaller and smaller and increasing complexity.The timing issues on SOC chips are becoming more and more complex.STA also become more complicated.STA is used for timing analysis of large integrated circuits.It is an important part of integrated circuit design and an important means to verify the correctness of integrated circuit design.Therefore,chip design is depended on correctly and quickly performing STA and quickly cloursing on timing issues in integrated circuits.Based on 12nm process SOC chips,this thesis completed the logic realization of the chip,and completed the physical design of the chip based on the back-end design tool Innovus.Combined with the OCV,AOCV and SOCV timing analysis methods,and applied to the physical design process of the chip.The timing information after the physical design of the chip is compared and analyzed from the timing analysis accuracy and the physical design cycle.The advantages and disadvantages of OCV,AOCV and SOCV timing analysis methods under advanced technology are verified.Then,for the non-sequential path that exists in the SOC chip in the physical design process,a constraint method is proposed to reduce the difficulty of timing closure caused by the unconstrained problem of the nonsequential path.Finally,based on the timing closure tool Tweaker,the analysis and repair strategies of timing violations on the SOC chip's setup hold time and non-sequence paths are studied.The timing analysis results show that the OCV timing analysis results are relatively pessimistic,and the difference is about 62.6%compared to the traditional timing results.Compared with the OCV analysis method,AOCV simulates the effect of on-chip deviation more accurately,and the AOCV timing analysis result is improved by about 30%compared with OCV.SOCV takes in account the influence of on-chip deviation randomness,which is more in line with the actual situation.Compared with AOCV,the SOCV timing analysis result is improved by about 20%.Comparative analysis shows that SOCV is a more suitable method for timing analysis under 12nm advanced technology.Then,for the non-sequential path in the SOC chip,a constraint method is proposed and applied to the physical design process of the chip.The result shows that the non-sequential path violation is reduced by 86%.Finally,in the timing closure phase,corresponding strategies and applicable scenarios for timing optimization are proposed for different types of timing violations.The work of this thesis reduces the workload of timing closure and greatly accelerates the design cycle of the chip.