Research On Key Technology Of Timing Closure For Wide Voltage Range Circuit

With the development of integrated circuit technology and applications,energy efficiency optimization has become an important challenge for IC design.Dynamic Voltage/Frequency Scaling(DVFS)is an effective way to achieve high performance and low power consumption and improve system energy efficiency.Wide range and fine grained power supply voltage adjustment,that is,wide voltage range operation,can achieve higher energy efficiency.However,wide voltage range circuit design is faced with two challenges,such as the serious variations at the low voltage and the complexity of the timing analysis in different working voltages.The existing timing variation tolerance technology has the disadvantages of a high error correction overhead.At present,there is no timing analysis method and timing model applicable to wide voltage range.Some people have proposed the idea of designing timing error tolerant and detection flip-flop and the timing analysis method of wide voltage range based on voltage sensitivity classification.Based on the above two timing problems under wide voltage,this paper has further studied and improved the existing technology.First of all,this paper is oriented to the timing analysis method of wide voltage range based on voltage sensitivity classification proposed by our group,and proposes a wide voltage delay-voltage analytical model and timing parameter voltage sensitivity model,as well as the corresponding modeling method,and establishes the analytic wide voltage timing model of the SMIC 40 nm process library's inverter and D flip-flop unit in the voltage range of 0.35V-1.1V.Compared with the original timing delay voltage model,the wide voltage timing voltage analytical model in this paper has a unified function form in the full voltage range instead of the subsection function of the original model,and solves the problem that the original model is not derivable at the segmentation point.Compared with the original voltage sensitivity model,the effect of the transition time of the input signal on the voltage change rate is considered in the modeling,and the precision of the voltage sensitivity model is improved.For the inverter,the maximum relative error of the time-delay analytical model is 39%,and the maximum relative error of the delay voltage sensitivity model is 31%.The measurement experiment based on the inverter chain shows the error of the timing voltage analytical model is 38%.The error of the voltage sensitivity model is 30%.Secondly,based on the existing timing error tolerant and detection idea,this paper systematically studies the design method of timing error tolerant and detection flip-flop,gives the timing constraint relation of the circuit,improves the circuit structure and transistor parameters,improves the performance,and evaluate the circuit based on the HSPICE simulation.And based on the designed timing error tolerant and detection flip-flop,the timing error correction scheme is designed and realized,and a complete set of timing variation tolerant solution is formed.The idea of combining timing error tolerance technology and error detection technology achieves a low overhead timing variation tolerant scheme.The timing error correction scheme designed in this paper continues to transfer the late data to the next stage circuit by the trigger of the timing error signal,and borrowing timing from the next stage circuit used to realize the timing error correction of the circuit.At the same time,timing error signals trigger clock signal switching then delay the arrival time of the next rising edge of the clock to make up the timing of the next stage circuit because of the timing borrowing.By applying the timing error tolerant and detection flip-flop to the test circuit of ISCAS' 89,the results show that the timing error tolerant and detection flip-flop reduces the error detection rate of the timing variation by 18% compared to the traditional error detection flip-flop.In this paper,the error correction scheme based on timing error tolerant and detection flip-flop has also reduced the timing overhead from multiple clock cycles to a clock cycle.