Static Timing Analysis And Optimization Of Digital Chip On 12nm Process

Static Timing Analysis(STA)is one of the most critical parts of digital integrated circuit implementation.It is used to verify the accuracy of the chip timing and to ensure that the chip can work normally.At the same time,with the process technology approaching to 7nm,the back-end implementation of the chip is facing greater challenges.Under the advanced process,an urgent problem is how to improve the reliability of static timing analysis results.In this thesis,the static timing analysis research is completed for a chip with TSMC 12 nm technology.The chip uses small-size advanced technology,with complex clock structure and multiple design levels,which makes it difficult in defining timing constraints.With the increasing randomness of device delay and high layout density,confirming the timing analysis results accuracy has become a key problem.(1)Considering the complexity of 12 nm chip,this thesis proposes an analysis plan to meet the static timing requirements,including using more accurate timing models and delay parameter format,building the PVT(Process,Voltage,Temperature)and MMMC(Multi Mode Multi Corner)environment,giving the timing constraints in SDC format.In this thesis,for the complex chip with advanced 12 nm process,in order to improve the accuracy of the timing analysis results,on the basis of the traditional timing analysis environment design scheme,oas file is added to extract parasitic parameters,and the netlist and timing constraints are checked for consistency.Compared with the timing analysis result without adding the oas file,WNS increased by 0.006 ns,and the number of violations increased by4.4%.In summary,after adding the oas file,the static timing analysis can effectively detect the violations caused by dummy.Through the consistency check,the accuracy of the clock relationship in SDC(Synopsys Design Constraint)format is increased.(2)Based on the timing analysis environment,three on chip variation modes,OCV(On Chip variation),AOCV(Advanced On Chip Variation)and POCV(Parametric On Chip Variation)are compared and analyzed from aspects such as model accuracy,timing analysis results,and calculation time.The research finds that under the 12 nm process,the delay of the OCV mode deviates greatly from the actual delay of the device,the device delay of the AOCV mode deviates less,but there is a greater deviation at the point where the logic depth is small,and the device delay of the POCV mode basically meets the actual delay.The timing analysis results are as follows.First of all,AOCV static timing analysis is used more time than OCV mode.At the same time,the worst delay in AOCV is reduced by 0.276 ns compared with OCV mode,and the total violation number is optimized by about 5.7%.Then,POCV uses similar calculation time as AOCV mode,and the worst delay is reduced by0.124 ns,the number of violation is optimized by about 6.4%.Furthermore,in the above three modes,two different delay calculation methods named GBA and PBA are compared.The research shows that the analysis result of AOCV PBA is partially better than POCV GBA,but the calculation time is nearly twice than POCV GBA.POCV PBA mode has a low optimization degree but consumes as much time as AOCV PBA mode.This thesis uses the POCV GBA mode as the first choice in the design implementation,which effectively improves the accuracy of timing analysis result under the 12 nm process,and takes power consumption,chip area,design timing and other aspects into consideration.(3)To optimize the timing violations based on the above analysis results,considering the complexity of the design,this thesis uses ECO(Engineering Change Order)on the data path and manually adjusts the clock path.Compared with the traditional ECO solution,the method adopted in this design can reduce a lot adjustments of std cells.Finally,the transition violations,setup violations,and hold violations are fixed,and the timing closure is achieved.The research in this thesis has been successfully taped out,and is currently being tested.The main innovative work of this thesis are as follows:(1)When this thesis extract the parasitic parameters,the oas file is added,therefore,the delay violations caused by dummy are effectively detected.In order to improve the timing analysis results accuracy,constraint consistency check link is added innovatively in the analysis flow.(2)This thesis proposes a reliable timing analysis scheme for digital chip with high logic complexity and high layout density on 12 nm process.In the optimization stage,the timing closure speed is accelerated.This thesis has a certain reference value to the static timing analysis work on the advanced process,and the research method also has applicability in the back-end design work.