Implementation Of Hierarchical Physical Design For HEVC Encoder Chip

As the feature size of integrated circuits continues to decrease and chip design complexity and integration increase,chip physical design faces many challenges.It not only needs to meet the chip timing,area,power consumption and design cycle requirements,but also to face the antenna effect,signal crosstalk,voltage drop and electromigration constraints.Especially for the physical design of VLSI,the flat design method can not always meet multiple design goals at the same time.Thus,it calls for a hierarchical design method or a new design method.The hierarchical physical design method shortens the design cycle and has important social and economic value.Compared with the H.264 encoding standard,the HEVC encoding chip can provide higher coding efficiency.Based on the completed the RTL code compiling of the HEVC encoding chip and simulation verification conducted by the the other members of our research group,this paper studied the entire physical design process from RTL code to GDSII format layout file generation,and aimed at shortening design cycle,timing closure,and reducing area,optimizing power consumption,eliminating antenna effects,solving signal crosstalk,clock tree network optimization,power network design optimization,Timing ECO,and other specific issues.In the stage of the chip's physical design,the hierarchical physical design method is used to complete the physical design of multiple sub-modules in parallel and realize the physical design of the entire chip.This method greatly shortens the physical design cycle of the chip.In order to achieve timing closure,logic synthesis based on physical information,path classification optimization,logical path optimization of hierarchical transparent interfaces,irregular grid clock networks,and Timing ECO are used.For the purpose of reducing power consumption,power optimization is implemented using methods such as power shutdown,multi-voltage,gating cells,and multi-threshold standard cells.In the layout planning phase,the wheel layout planning method is used to reduce the difficulty of the submodule placement,and the multi-layer power ring structure is adopted to reduce the area and satisfy the voltage drop requirement.To avoid the chip function failure caused by signal crosstalk,the entire physical design process is considered to prevent signal crosstalk effects.In the routing phase,the antenna effect is eliminated by the routing jump layer method and insertion protection diodes.In the design stage of manufacturability,inserting filling cells,filling metals,redundant vias,and extended interconnects are added to the layout after routing for improving chip yield.This paper implements the physical design of the HEVC encoder chip,with a chip size of around 17.3M gates.It meets the requirements of the design and manufacturing process through formal verification,static timing analysis,design rule checking,layout and schematic consistency check,and achieves the following indicators:the area is 34798201 ?m2,working frequency is 200MHz,and the power consumption is 109.6mW,and the sum of voltage drop and ground voltage rebound is less than 3%VDD.In the design stage of manufacturability,inserting filling cells,filling metals,redundant vias,and extended interconnects are added to the layout after routing to improve chip yield.