Jane Instruction Microprocessor (risc) Process Design

Now, the design and manufacture technology of VLSI have been perfected. A great progress has been made in the design of MPU, especially embedded MPU, thanks to its low power consumption and high performance. The research and development of RISC CPU, as embedded system, is vital for the development of SOC (System On a Chip).This subject has completed the whole design of the 32-bit RISC MPU based on the MIPSII instruction system, from the system level hardware description, simulation & synthesis verification and the place and route to the placement optimization.The whole design flow of this subject reflects my attempt in the field of VLSI SOC design methodology, especially in the innovation of the design process organization. Many design tools of Synopsys have been used, including VCS, DESIGN COMPILER, FORMALITY, PHYSICAL COMPILE, FLOOR PLAN COMPILE,CTS, PRIMTIME, STAR-RCXT and ASTRO.Firstly, the design begins with the finish and verification of code level design and the logic synthesis. Based on area constraint and timing constraint, area constraint and timing logic constraint have been finished. Then physical design process is developed. Physical design flow begins with physical compile, followed by the floor plan such as 10 unit and the synthesis of CTS. Place and route have been completed with ASTRO.After the primtime simulation and parastic extraction in the area of place and route, plan and adjustment in detail have been finished according to the simulation result and parameters. Formality of gate netlist, netlist after physical compile, netlist after floor plan, netlist after CTS is finished. By the adjustment of the entire flow, the problems of SI (single integrate), crosstalk and parastic extraction have been analyzed and worked out. Widening the distance between the signal wires, taking shield measures and detecting SI with the parameter extraction and analysis tools. In the selecting of drivers, we take buffers to divide the long wire for the decrease of wires and coupling capacitance. Through decreasing input load of buffer to the singleload, we can ensure the realization of bottom plan and optimization by the small modification in the place and route of buffers. By adding primetime analysis in the design flow, the problems of noise and delay are worked out The procedures solving the problems of crosstalk and timing are put into one flow. Finally, by repeat experiments and designs, the full flow design of RISC has been finished. The research and work of this design have system and operation characteristics and the design foundation of 64-bit RSIC MPU has been made. This research is supported by Semiconductor Manufacturing International Corporation and Trident Multimedia Technologies(Shanghai)Co., Ltd.