The Research Of Soc Low Power Technology And Apply On The Physical Design

Low power design is attracting a great deal of attention in VLSI digital design, especially for portable systems and high performance systems. As the process of integrated circuits has entered into deep submicron and ultra deep submicron era, power dissipation has become the critical factors to restrict the performance of the chip. Low power dissipation can save the cost of the packaging and prolong the battery life of the portable devices. Therefore developing the low power technology is an important direction for the future IC designs.The thesis firstly studied and analyzed the main power source of the CMOS circuit. The power source contains dynamic power and static power, the dynamic power contains switch power and internal power, meanwhile the sub-threshold leakage current is the main source of the static power. Then various lower power design methodologies at different levels of abstraction are analyzed. The hierarchical low power design methodologies include process level, circuit level, gate level, RTL level, architectural level and system level. The process level mainly analyzes the influence of the packaging and manufacture technology to the power, the circuit level mainly analyzed the technology of the multi-supply voltage (MSV), also analyzed the path balance technology. The gate level low power technology mainly analyzed gate level power optimization and multi-threshold CMOS circuit optimization. The RTL level mainly analyzed clock gating low power technology. The architectural level analyzed parallel structure and pipeline structure to save the power. The system level analyzed power gating technology to reduce the leakage power. The higher the abstract level is, the more power can save.Finally, the flow of the digital backend is explained according to the physical design of the reconfigurable video decoder chip which is based on TSMC65nm LP process. The place and route of the chip is finished by the Synopsys tool IC compiler, which is the most important step of the digital backend. The quality of the place and route directly influences the performance of the chip. The reconfigurable video decoder chip adopts clock gating technology to reduce the dynamic power and multi-threshold technology to reduce the static power. The multi-threshold technology is used throughout the whole process of the chip design, which includes logic synthesis process and place and route process. Balancing the timing optimization and power optimization is achieved perfectly.