A FPGA Based PCIE DMA Subsystem For 3D CT Image Reconstruction

Spiral cone-beam CT(Computer Tomography) is a widely used medical imaging system in the world. Accurate 3D spiral cone-beam CT imaging can locate the anatomical position of the tumor and create the image. So it is one of the most effective technologies to solve practical orientation of Clinical Oncology. But the precise 3D spiral cone-beam CT imaging need enormous computing capacity. The ordinary computers require a long computing time. Using FPGA as a hardware accelerator can meet the needs of the calculation time under clinical conditions and can rapidly complete the calculations of accurate 3D spiral cone-beam CT imaging.As a PCI Express(PCIe in short) DMA Subsystem of spiral cone-beam 3D reconstruction of the FPGA hardware acceleration system in the author's laboratory, the main objective is to solve the problem of massive data transmission between PC memory and FPGA hardware accelerator memory. Using the DMA controller based on high-speed PCIe bus, massive raw data are transfered between the host computer memory and DDR2 memory of the accelerator with satisfied requirement.First, this dissertation describes the principle of spiral cone-beam CT 3D reconstruction of FPGA hardware acceleration system. Then functions are partitioned based on the analysis of the role of PCIe DMA subsystem in the whole acceleration system. Based on in-depth study of the PCIe configuration mechanisms, transaction type and transaction layer packet format, the PCIe DMA controller architecture is defined. The whole design is partitioned into register file module, controlling module CTR_CTRL, receiving engine RX_Engine, sending engine TX_Engine and other sub-modules.Then the PCIe DMA controller is implemented in RTL-level Verilog and the test platform for functional simulation is build up.Second, the research about PCIe DMA controller device driver is designed based on WinDriver for 3D reconstruction accelerate system requirements, combined with the key meaning and functions of PCIe DMA controller registers, using Microsoft VC6.0 platform to design the device driver.Finally, a PCIe DMA hardware and software subsystems is build up and verified for FPGA-system testing. Test results show that PCIe DMA controller can work as desired, and its functionality and performance has reached the system requirements.