Design Of High-Speed Data Transmission Channel Based On PCIE Bus

With the rapid development of wireless communication technology and digital processing technology,more and more developers use software radio to design communication equipment.The design concept of software radio is to realize the signal processing with software program as much as possible.With the help of the characteristics of software programming,the communication equipment has the advantages of high flexibility,high reliability and strong expandability.However,with the commercialization of 5G and other emerging wireless communication technologies,The amount of data transferred in software radio products is increasing,and the real-time performance is becoming stronger and stronger,with more and more data transmission channels.The traditional transmission bus used in software radio platform,such as USB,Ethernet and so on,has limited transmission bandwidth and is easy to form a bottleneck in data transmission.As the latest computer bus standard,PCIe bus can meet the data transmission requirements of software radio,and has rich hardware support,which can be applied to most personal computers.Therefore,this thesis designs a high-speed data transmission channel based on PCIE bus for the software radio platform and encapsulates it into a reusable IP core.Firstly,the protocol of PCIE bus was studied in depth.On this basis,the system framework of data transmission between application logic on FPGA and computer was established.The design of data transmission channel focuses on the application logic on FPGA,which is divided into DMA interface logic and DMA control logic.In addition,the structure of multi-channel signal transceiver as one of the application environments is introduced,which provides a theoretical basis for the subsequent design and testing.Secondly,the modules and software programs of the application logic of the data transmission channel are designed and implemented.Using Verilog HDL to design RTL for DMA interface logic and DMA control logic.In DMA control logic,a DDR3 storage controller based on channel wheel cycle is designed to solve the conflict when multiple channels access a DDR3 memory at the same time.A dynamic priority arbitration mechanism based on signal bandwidth is designed to optimize the transmission efficiency for multi-channel transmission with dynamic variable rate in the wireless data transmission.Design the software program of the data transmission channel from two parts: driver program design and application program design.Finally,the data transmission channel is actually tested.In terms of functional verification,vivado's built-in logic analyzer is used to test the functions of the DMA control logic module in the application logic.In the aspect of performance verification,the software program is used to test the transmission bandwidth of the data transmission channel.In terms of overall test,the actual working environment of the software radio platform is simulated,and the overall function of the data transmission channel is verified.The results show that the data transmission channel designed in this thesis can reach 2624MB/s in single channel and 2175MB/s in 32 channel,which can meet the demand of large transmission volume and multi-channel data transmission in software radio environment and has good engineering application value.