Design Of Data Acquisition System Based On FPGA For EMMC Storage,PCIe And Ethernet Transmission

With the continuous development of the measurement and control industry,in many signal acquisition applications,the acquisition equipment needs to perform multi-channel,high synchronization,high sampling rate,high precision,high throughput,and real-time transmission of the measurement signals.Therefore,designing a multi-channel acquisition system with data storage and transmission functions has significant engineering application value.Based on the 128-channel synchronous acquisition design of the rotor blade surface pressure signal,this paper studies the estimation and correction of acquisition system for the channel mismatch effects,eMMC storage,Ethernet data transmission,and PCIe data transmission.It mainly includes:1)Analysis of multi-channel acquisition phase matching offset caused by ADC sampling clock delay error;2)Research on JESD84-B51 specification and FPGA-based data storage controller design;3)TCP data communication design based on Ethernet chip W5500 and PCIe data transmission design integrated with Xilinx IP core integrated RIFFA2.0 framework.Firstly,this paper proposes a system design scheme based on the applied scenario.The structure of the entire scheme design is mainly composed of a signal acquisition card and a data storage transmission master control card.Among them,the signal acquisition card is mainly the design of signal amplification,filtering,ADC and control logic module.The data storage transmission master control card is mainly designed for master-slave data communication,data processing,PCIe data transmission,eMMC data storage,and Ethernet communication.Then this article analyzes the characteristics of the acquisition system,which mainly analyzes the ADC system model,performance parameters,mismatches and multi-channel phase matching.Then ADC system model was used to quantitatively analyze the effects of offset error,gain error,and clock delay error on the frequency domain of the collected data.Secondly,the eMMC 5.0 specification protocol is studied.The protocol specifies the working registers of the storage device,the working mode of the device,the data communication interface,and the read-write control timing.Based on this protocol,an FPGA-based eMMC data storage controller is designed.The controller mainly includes an initialization module,a command communication module,a working state processing module,and a data read-write driver module.Then according to actual needs,this acquisition system designed two data transmission methods,one is the TCP data communication combined with the Ethernet chip W5500,and the other is the PCIe data transmission design integrated with the Xilinx IP core and integrated RIFFA2.0 framework.Ethernet transmission uses the network chip W5500 as the TCP communication connection controller.The main controller is responsible for reading and writing the chip's registers to achieve data transmission.PCIe data transmission uses the IP core in Xilin FPGA to implement the physical layer data processing of PCIe,and the data link layer and transaction layer are implemented by the RJFFA2.0 integration module.Finally,it mainly tests each module in the design data acquisition system,which includes the acquisition card part,data storage part,and data transmission part.The acquisition card mainly verifies the configuration of the gain and the data return function.The data storage mainly verifies the read and write speed and accuracy of the data.The data transmission mainly verifies the TCP communication and PCIe data transmission.The test results show that a single acquisition card can meet the simultaneous acquisition of 16 channels of200KSPS,and a total of 128 channels of 8 acquisition cards can simultaneously acquire a data volume of 76MB/s.The eMMC storage controller can achieve a read and write rate of up to 104MB/s,the W5500 network communication rate is measured at 22Mb/s,and PCIe data transmission can reach a total transmission bandwidth of 3 GB/s.