Implementionof PCIe High Speed Transmission Systemof RS Encoderand Decoder Data Basedon FPGA

With the development of technological eraof the times, the processing speedof many hardware devices such as computers are becoming higher andhigher.What’s more, with the improvement of the performance of several miningequipment, high-speed and high-capacity data is to be transmitted fast, reliably,real-time in the test. Some parallel bus or AMBA bus can not meet the highrequirements. However, PCIe bus is a serial bus to achieve the highest data rateat present. PCIe architecture is inherited the most useful features of asecond-generation bus architecture, and is used some new technologicalachievements,these make it possible to achieve high data throughput level. Basedon this background, a high-speed data transmission system based on PCIe bus isdesigned.in addition, RS code has been widely used in the field ofcommunication as one of the error correcting code technology. We detect thetransmission of RS code data because its coding algorithm is relatively simpleand effective. Achieve the RS encoding through the Matlab and achieve the RSdecoding through the Xilinx’s rs_decoder IPCore.The main objective of this paper is to achieve the high speed serial datatransmission system based on PCIe bus. The system design is designedrespectively two parts. On the part of the hardware, we firstly analyze the PCIeprotocol, and then give the design scheme of the whole system. The hardwaredesign of the data transmission system is designed by the modular structure,divided into the generating and the calling of PCIe IPCore, PCIe user logic, datacache and RS decoder. Use the PCIe core in the FPGA to implement the PCIe busprotocol and use the verilogHDL to realize the PCIe bus endpoint,FIFO cache,the interface between the PCIe bus logic and RS decoder and interrupt controlfunction. PCIe bus endpoints logic is divided into receiving module, transmitingmodule, DMAmodule.The various functional modules are strictly functionalsimulated after the coding. On the software part, the driver of PCIe device basedon Linux environment is designed. At the end of this paper, we establish asoftware and hardware verification environment of the data transmission systemand condut a FPGA system testing. The results displaythe data transmissionsystem realizes the expected functions, transports data stably and reliabl y.