Unified Verification Framework Automation And Test Standardization With UVM

With the continuous improvement of integrated circuit process technology and design capability,So C system becomes more and more complicated.In order to ensure the normal tapeout,the workload of IC verification continues to increase.IC verification has became a key factor affecting So C develop efficiency.However,now in the So C verification,it takes a long time to develop verification environment,and the reusability of the verification environment is poor.At the same time,Verification test cases have poor readability,and poor reusability.These problems all lead to low verification efficiency.Therefore,the purpose of this paper is to develop a tool for automatically generating verification environment so as to quickly build a verification environment with high reusability.And simple standardized test cases designed in this paper improves test case development and reuse efficiency.The tool for automatically generating verification environment is mainly composed of a standardized verification environment system and a code generation system.Based on UVM and commonly used interface VIP,a configurable hierarchical network verification environment is designed in standardized verification environment system.Based on Mako templates and Python script,a simple automatic code generator for verification environment is designed in code generation system.And based on common operations in verification scenario,a series of standardized test instruction sets for clock,reset,register,IOC,and bus operation are defined.Finally,this paper realized that for any given design under test,a highly reusableverification environment will be built quickly based on code generation system.And ICverification engineers can build verification scenario quickly with the standardized testinstruction sets.The verification strategy designed in this paper is applied to actual digital IC verification project.For any design under test,the verification environment can be seted up within half a working day with the automatic tool.The application's results show that the tool improves the efficiency of the verification environment by at least 70%,and improves the test case development efficiency by at least 30%.Compared with the traditional verification environment,the generated verification environment in this paper has high reliability and high reusability.In addition,the standardized test cases proposed in this paper also have high readability and high reusability.The innovative environment structure design in this paper provides new ideas and feasible solutions for improving the efficiency of IC verification.