Automatic Test Pattern Generation And The Functionality Verification Environment

At present, the development of IC manufactural technology is continuous and the IC design methodology is updating. With automation of IC design improvement, IC scale becomes larger, the correctness of each chip should be taken into the first consideration for every IC design engineer. Due to the IC verification and test becomes more and more complicated, production test cost is higher than before, and the pressure on shorten product time to market becomes more and more, those result in the traditional method to generate functional test pattern can hardly satisfy modern standard. Therefore, how to quickly generate accurate functional test pattern has turned to be the important factor in lower production test cost and shorter time to market.This paper starts with the essential theory about IC verification and test, introduces different verification techniques, ATE and test classification in brief, especially describes test pattern format and its generation method. Based on these facts, this paper analyzes the basic principles about input stimulus, and proposes a new functionality verification environment to improve the efficiency and correctness of test pattern generation. And the environment is put into practice, so the target is implemented finally.