The Verification Environment Of SERDES Based On Open Vera

The work of this thesis is based on one of the data traffic chips developed by Hisilicon Inc, SERDES is the high speed IO interface. The function verification platform of SERDES interface module has been completed and tested, using OpenVera advanced hardware verification language.First of all, the importance and current situation of chip verification task are introduced briefly, and both simulation and formal function verification methods are analysed and compared. In succession, the hiberarchy function verification platform of SERDES interface module is explained in detail, and how to realize each of function modules in the platform is showed. Based on this, test-piont decomposion of SERDES module is accomplished, and both direct test and constraint random test are used to verify it. Finally, the all-round function coverage is achieved.Now, the chip function verification task has already been completed. And the simulation results showed that the performances of the chip were excellent and can meet the functional specifications.