An Automatic Verification Method Based On Network On Chip

With the increase of the number of IP cores in SOC,traditional on-chip interconnect buses cannot meet requirements of system performance due to poor scalability,high latency,and problems such as area and power.For a scalable interconnect structure,the Network on Chip solves problems faced by traditional buses.According to functional verification of the Network on Chip,this thesis combies Specman-Elite and bus e VC to build a highly scalable,reusable Testbench,and an automatic verification method is proposed.This thesis combines Intel's mobile baseband chip to introduce the verification environment of the on-chip network in detail.The verification environment is based on e-language encoding and consists of two parts: first,bus e VCs with standard protocol directly provided by the design manufacturer;second,in order to enable the bus e VC to simulate the IP interface,build verification environment that can uniformly configure the e VCs,namely NVE.NVE is a very flexible and reusable verification environment,which will not be affected by adding or removing some peripheral modules in the topology.NVE has the following advantages: first,in the aspect of inheriting RTL code,NVE's database can describe the port information about the topology.As long as the database captures these port information,the database can automatically complete the configuration of the verification environment;then,in the aspect of simulation performance,working topology can be used to specify the corresponding topology according to actual needs,in order to shorten the time consumed by NVE in functional verification.Finally,it is simple and highly efficient to verify the environment,In the process of building Testbench of the Network on Chip,an automatic verification method for the NVE is proposed,because the traditional method is inefficient and errorprone.It uses the Perl script tool to automate the completion of the verification environment.The selection of parameters,the design of templates and the implementation of codings will be elaborated in the thesis.This method has been applied to digital chip verification projects.This results show that the automatic verification method has improved the efficiency of the Testbench by at least 70%,and significantly reduces investment costs in human resources.Moreover,compared with the traditional verification method,the verification environment built with script tools has characteristics of high reliability and high reusability.Therefore,it's highly practical significant to use this automatic verification method proposed in this thesis,this method not only improves the efficiency of chip verification,shortens the cycle of chip development,but also provides a certain reference value for similar design and verification work.