Physical Design Of High-Speed Interface And Research In Placement

Physical design is an indispensable step in the design of integrated circuits.It is not only related to whether the function of the integrated circuit can be realized,but also to the design cycle,cost,power consumption and reliability.It is very important and has a very important practical significance to study the physical design under advanced technology to speed up the timing of convergence,shorten the design cycle,improve the design quality and reliability of chip.In this paper,we comleted the physical design of two high-speed interfaces(SRIO high-speed interface and DDR3 memory interface)in a high-performance DSP chip,and a wirelength-driven placement algorithm that face to engineering is proposed and implemented.In the physical design of the SRIO high-speed interface,the backbone of the functional clock tree is analyzed and designed,and the clocks related to the internal Serdes IP are planned reasonably.Then,the timing statistic script is designed for the imbalance of the test clock tree.It is proved effective in reducing the number of cell insertion in the timing closure.Finally,the board-level co-simulation is carried out to evaluate the jitter and return loss of.Design results show that the maximum frequency of the interface meet 1.1GHz,and achieve the standard protocol requirementsIn the physical design of DDR3 memory interface,the floorplan,clock tree and timing convergence method of DDR3 memory interface are proposed and implemented.In the floorplan stage,the layout size of DDR3 and the planning of macros,IO units are determined considering the factors such as area and timing.In the timing convergence stage,we analyze the clock and path structure of DDR3,and make precise manual planning for the critical path.we also realized the automation skew check script,controll the bus skew within 40 ps.The experimental results show that the design of this paper achieves the goal of frequency 533 MHz,maximum data rate 2133 Mbps.In addition,a wirelength-driven placement algorithm based on simulated annealing and analytic method is implemented in the place stage of physical design.In the initial stage of the placement,the simulated annealing algorithm is proposed to obtain the initial result with uniform density and good wirelength.In the subsequent stage,the multi-level optimization strategy is used.,The conjugate gradient method is used to optimize the line length and density continually.In order to verify the practicability of the algorithm in the engineering field,this paper extracts some modules in the project as examples and designs the comparative experiment.Experimental results show that the proposed algorithm is equivalent to the EDA tool in most cases and reveals high performance in some modules.